# SPDX-License-Identifier: GPL-2.0-or-later

# STMicroelectronics STM32MP13x (Single Cortex-A7)
# http://www.st.com/stm32mp1

# HLA does not support custom CSW nor AP other than 0
if { [using_hla] } {
	echo "ERROR: HLA transport cannot work with this target."
	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp13x_dk.cfg\"."
	shutdown
}

source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32mp13x
}

if { [info exists CPUTAPID] } {
	set _CPUTAPID $CPUTAPID
} else {
	if { [using_jtag] } {
		set _CPUTAPID 0x6ba00477
	} else {
		set _CPUTAPID 0x6ba02477
	}
}

# Chip Level TAP Controller, only in jtag mode
if { [info exists CLCTAPID] } {
	set _CLCTAPID $CLCTAPID
} else {
	set _CLCTAPID 0x06501041
}

swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
if { [using_jtag] } {
	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
}

dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack

# NOTE: keep ap-num and dbgbase to speed-up examine after reset
# NOTE: do not change the order of target create
target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine

$_CHIPNAME.cpu cortex_a maskisr on
$_CHIPNAME.cpu cortex_a dacrfixup on

# interface does not work while srst is asserted
# this is target specific, valid for every board
# srst resets the debug unit, behavior equivalent to "srst_pulls_trst"
reset_config srst_gates_jtag srst_pulls_trst

adapter speed 5000
adapter srst pulse_width 200
# bootrom has an internal timeout of 1 second for detecting the boot flash.
# wait at least 1 second to guarantee we are out of bootrom
adapter srst delay 1100

add_help_text axi_secure "Set secure mode for following AXI accesses"
proc axi_secure {} {
	$::_CHIPNAME.dap apsel 0
	$::_CHIPNAME.dap apcsw 0x10006000
}

add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
proc axi_nsecure {} {
	$::_CHIPNAME.dap apsel 0
	$::_CHIPNAME.dap apcsw 0x30006000
}

axi_secure

# mmw with target selection
proc target_mmw {target reg setbits clearbits} {
	set val [eval $target read_memory $reg 32 1]
	set val [expr {($val & ~$clearbits) | $setbits}]
	eval $target mww $reg $val
}

lappend _telnet_autocomplete_skip _enable_debug
# Uses AP1
proc _enable_debug {} {
	# keep clock enabled in low-power
	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
	# freeze watchdog 1 and 2 on core halted
	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
}

lappend _telnet_autocomplete_skip _handshake_with_wrapper
# Uses AP1
proc _handshake_with_wrapper { halt } {
	set dbgmcu_cr 0
	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
		return
	}

	if { $halt } {
		$::_CHIPNAME.ap1 arp_halt
		$::_CHIPNAME.ap1 mww 0xe00d0300 0
		target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
	}

	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
}

# FIXME: most of handlers below will be removed once reset framework get merged
$_CHIPNAME.ap1 configure -event reset-assert-post {
	adapter assert srst
}

$_CHIPNAME.ap1 configure -event reset-deassert-pre {
	adapter deassert srst deassert trst
	$::_CHIPNAME.ap1 arp_examine
	_handshake_with_wrapper $halt
	_enable_debug
	$::_CHIPNAME.cpu arp_examine
	if { $halt } {
		$::_CHIPNAME.cpu arp_halt
	}
}

$_CHIPNAME.ap1 configure -event examine-end {
	_enable_debug
	$::_CHIPNAME.cpu arp_examine
}
