# SPDX-License-Identifier: GPL-2.0-or-later
# maxim Integrated OpenOCD target configuration file

# reset pin configuration
reset_config none
adapter_nsrst_delay 200
adapter_nsrst_assert_width 200

# Set flash parameters
set FLASH_BASE 0x10000000
set FLASH_SIZE 0x60000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
set FLASH_OPTIONS 0x01

# Use Serial Wire Debug
transport select swd

source [find target/max32xxx.cfg]

# Early revisions of the MAX32670 will disable SWD upon reset. There are reserved address locations
# in the ROM code that can be used to insert breakpoints.
# This workaround will enable SWD for affected revisions.
$_CHIPNAME.cpu configure -event reset-assert-pre {
	if {$halt} {catch {bp 0x00002174 2 hw}}
}

$_CHIPNAME.cpu configure -event reset-deassert-post {
	if {$halt} {
		$::_CHIPNAME.cpu arp_poll
		$::_CHIPNAME.cpu arp_poll
		$::_CHIPNAME.cpu arp_halt
		rbp 0x00002174
	}
}
