# SPDX-License-Identifier: GPL-2.0-or-later

#
# Configuration file for Artery AT32F4x family.
#
# https://www.arterychip.com/en/product/
#

# AT32F4x devices support JTAG and SWD transport.
source [find target/swj-dp.tcl]

if { [info exists CHIPNAME] } {
   set _CHIPNAME $CHIPNAME
} else {
   set _CHIPNAME at32f4x
}

# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1000
}

if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   if { [using_jtag] } {
      set _CPUTAPID 0x4ba00477
   } {
      set _CPUTAPID 0x1ba01477
   }
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE

set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME artery 0x08000000 0 0 0 $_TARGETNAME

adapter speed 1000

if {![using_hla]} {
    cortex_m reset_config sysresetreq
}
