# SPDX-License-Identifier: GPL-2.0-or-later

# script for stm32c0x family
#
# stm32c0 devices support SWD transports only.
#

source [find target/swj-dp.tcl]
source [find mem_helper.tcl]

if { [info exists CHIPNAME] } {
	set _CHIPNAME $CHIPNAME
} else {
	set _CHIPNAME stm32c0x
}

set _ENDIAN little

# Work-area is a space in RAM used for flash programming
# By default use 6kB
if { [info exists WORKAREASIZE] } {
   set _WORKAREASIZE $WORKAREASIZE
} else {
   set _WORKAREASIZE 0x1800
}

#jtag scan chain
if { [info exists CPUTAPID] } {
   set _CPUTAPID $CPUTAPID
} else {
   # SWD IDCODE (single drop, arm)
   set _CPUTAPID 0x0bc11477
}

swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap

$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp   stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME

# reasonable default
adapter speed 2000

adapter srst delay 100
if {[using_jtag]} {
	jtag_ntrst_delay 100
}

reset_config srst_nogate

if {![using_hla]} {
	# if srst is not fitted use SYSRESETREQ to
	# perform a soft reset
	cortex_m reset_config sysresetreq
}

$_TARGETNAME configure -event examine-end {
	# Enable DBGMCU clock
	# RCC_APB1ENR |= DBGMCUEN
	mmw 0x4002103C 0x08000000 0

	# Enable debug during low power modes (uses more power)
	# DBGMCU_CR |= DBG_STANDBY | DBG_STOP
	mmw 0x40015804 0x00000006 0

	# Stop watchdog counters during halt
	# DBGMCU_APB1_FZ |= DBG_WDGLS_STOP | DBG_WWDG_STOP
	mmw 0x40015808 0x00001800 0
}
