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openocd: drop empty string suffix from format strings

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Format strings are often split to allow using the conversion
specifiers macros from <inttypes.h>.
When the format string ends with one of such macros, there is no
need to add an empty string "" after the macro.

In current code we have 203 cases of empty string present, against
1159 cases of string ending with the macro.

Uniform the style across OpenOCD by removing the empty string.

Don't modify the files 'angie.c' and 'max32xxx.c' as they are
already changed by other independent commits.

Change-Id: I23f1120101ce1da67c6578635fc6507a58c803e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9065
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2025-08-01 17:06:05 +02:00
parent 9fe3780432
commit 003cb92cd5
52 changed files with 200 additions and 200 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/flash/nor/at91sam7.c
+4 -4
View File
@@ -291,14 +291,14 @@ static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t wait
while ((!((status = at91sam7_get_flash_status(bank->target,
bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
LOG_DEBUG("status[%i]: 0x%" PRIx32, (int)bank->bank_number, status);
alive_sleep(1);
}
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
LOG_DEBUG("status[%i]: 0x%" PRIx32, bank->bank_number, status);
if (status & 0x0C) {
LOG_ERROR("status register: 0x%" PRIx32 "", status);
LOG_ERROR("status register: 0x%" PRIx32, status);
if (status & 0x4)
LOG_ERROR("Lock Error Bit Detected, Operation Abort");
if (status & 0x8)
@@ -915,7 +915,7 @@ static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32
dst_min_alignment = at91sam7_info->pagesize;
if (offset % dst_min_alignment) {
LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32,
offset,
dst_min_alignment);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
src/flash/nor/atsamv.c
+1 -1
View File
@@ -310,7 +310,7 @@ static int samv_probe(struct flash_bank *bank)
int r = samv_get_device_id(bank, &device_id);
if (r != ERROR_OK)
return r;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
LOG_INFO("device id = 0x%08" PRIx32, device_id);
uint8_t eproc = (device_id >> 5) & 0x7;
if (eproc != 0) {
src/flash/nor/avrf.c
+7 -7
View File
@@ -126,7 +126,7 @@ static int avr_jtagprg_chiperase(struct avr_common *avr)
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
LOG_DEBUG("poll_value = 0x%04" PRIx32, poll_value);
} while (!(poll_value & 0x0200));
return ERROR_OK;
@@ -187,7 +187,7 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr,
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
LOG_DEBUG("poll_value = 0x%04" PRIx32, poll_value);
} while (!(poll_value & 0x0200));
return ERROR_OK;
@@ -253,8 +253,8 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
LOG_DEBUG("count is %" PRIu32 "", count);
LOG_DEBUG("offset is 0x%08" PRIx32, offset);
LOG_DEBUG("count is %" PRIu32, count);
if (avr_jtagprg_enterprogmode(avr) != ERROR_OK)
return ERROR_FAIL;
@@ -308,7 +308,7 @@ static int avrf_probe(struct flash_bank *bank)
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
LOG_INFO("device id = 0x%08" PRIx32, device_id);
if (EXTRACT_MFG(device_id) != 0x1F)
LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
EXTRACT_MFG(device_id),
@@ -373,7 +373,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
LOG_INFO("device id = 0x%08" PRIx32, device_id);
if (EXTRACT_MFG(device_id) != 0x1F)
LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
EXTRACT_MFG(device_id),
@@ -390,7 +390,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
if (avr_info) {
/* chip found */
command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32 "", avr_info->name,
command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32, avr_info->name,
EXTRACT_VER(device_id));
return ERROR_OK;
} else {
src/flash/nor/cfi.c
+2 -2
View File
@@ -2722,7 +2722,7 @@ int cfi_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(
"erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
"erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32,
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
(cfi_info->erase_region_info[i] >> 16) * 256);
@@ -2849,7 +2849,7 @@ int cfi_probe(struct flash_bank *bank)
}
if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width)) {
LOG_WARNING(
"CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "",
"CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32,
(cfi_info->dev_size * bank->bus_width / bank->chip_width),
offset);
}
src/flash/nor/efm32.c
+1 -1
View File
@@ -430,7 +430,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout,
if (ret != ERROR_OK)
break;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if (((status & wait_mask) == 0) && (wait_for_set == 0))
break;
src/flash/nor/em357.c
+1 -1
View File
@@ -115,7 +115,7 @@ static int em357_wait_status_busy(struct flash_bank *bank, int timeout)
retval = em357_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_BSY) == 0)
break;
if (timeout-- <= 0) {
src/flash/nor/lpc288x.c
+2 -2
View File
@@ -279,7 +279,7 @@ static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
/* all writes must start on a sector boundary... */
if (offset % bank->sectors[i].size) {
LOG_INFO(
"offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
"offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32,
offset,
bank->sectors[i].size);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
@@ -293,7 +293,7 @@ static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
/* Range check... */
if (first_sector == 0xffffffff || last_sector == 0xffffffff) {
LOG_INFO("Range check failed %" PRIx32 " %" PRIx32 "", offset, count);
LOG_INFO("Range check failed %" PRIx32 " %" PRIx32, offset, count);
return ERROR_FLASH_DST_OUT_OF_BANK;
}
src/flash/nor/mspm0.c
+1 -1
View File
@@ -429,7 +429,7 @@ static int mspm0_read_part_info(struct flash_bank *bank)
LOG_WARNING("Unknown Device ID[0x%" PRIx32 "], cannot identify target",
did);
LOG_DEBUG("did 0x%" PRIx32 ", traceid 0x%" PRIx32 ", userid 0x%" PRIx32
", flashram 0x%" PRIx32 "", did, mspm0_info->traceid, userid,
", flashram 0x%" PRIx32, did, mspm0_info->traceid, userid,
flashram);
return ERROR_FLASH_OPERATION_FAILED;
}
src/flash/nor/numicro.c
+5 -5
View File
@@ -567,7 +567,7 @@ static int numicro_reg_unlock(struct target *target)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected);
LOG_DEBUG("protected = 0x%08" PRIx32, is_protected);
if (is_protected == 0) { /* means protected - so unlock it */
/* unlock flash registers */
retval = target_write_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, REG_KEY1);
@@ -828,7 +828,7 @@ static int numicro_protect_check(struct flash_bank *bank)
numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0 - m_address_bias_offset, 0, &config[0]);
numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1 - m_address_bias_offset, 0, &config[1]);
LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]);
LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32, config[0], config[1]);
if ((config[0] & (1<<7)) == 0)
LOG_INFO("CBS=0: Boot From LPROM");
@@ -908,7 +908,7 @@ static int numicro_erase(struct flash_bank *bank, unsigned int first,
if (retval != ERROR_OK)
return retval;
if ((status & ISPCON_ISPFF) != 0) {
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
LOG_DEBUG("failure: 0x%" PRIx32, status);
/* if bit is set, then must write to it to clear it. */
retval = target_write_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, (status | ISPCON_ISPFF));
if (retval != ERROR_OK)
@@ -1007,7 +1007,7 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
return retval;
if ((status & ISPCON_ISPFF) != 0) {
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
LOG_DEBUG("failure: 0x%" PRIx32, status);
/* if bit is set, then must write to it to clear it. */
retval = target_write_u32(target,
NUMICRO_FLASH_ISPCON - m_address_bias_offset,
@@ -1037,7 +1037,7 @@ static int numicro_get_cpu_type(struct target *target, const struct numicro_cpu_
return ERROR_FLASH_OPERATION_FAILED;
}
LOG_INFO("Device ID: 0x%08" PRIx32 "", part_id);
LOG_INFO("Device ID: 0x%08" PRIx32, part_id);
/* search part numbers */
for (size_t i = 0; i < ARRAY_SIZE(numicro_parts); i++) {
if (part_id == numicro_parts[i].partid) {
src/flash/nor/ocl.c
+4 -4
View File
@@ -82,9 +82,9 @@ static int ocl_erase(struct flash_bank *bank, unsigned int first,
if (dcc_buffer[1] != OCL_CMD_DONE) {
if (dcc_buffer[0] == OCL_ERASE_ALL)
LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08" PRIx32 "", dcc_buffer[1]);
LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08" PRIx32, dcc_buffer[1]);
else
LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08" PRIx32 "", dcc_buffer[1]);
LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08" PRIx32, dcc_buffer[1]);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -178,7 +178,7 @@ static int ocl_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
}
if (dcc_buffer[0] != OCL_CMD_DONE) {
LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08" PRIx32 "", dcc_buffer[0]);
LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08" PRIx32, dcc_buffer[0]);
free(dcc_buffer);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -217,7 +217,7 @@ static int ocl_probe(struct flash_bank *bank)
return retval;
if (dcc_buffer[0] != OCL_CMD_DONE) {
LOG_ERROR("loader response to OCL_PROBE 0x%08" PRIx32 "", dcc_buffer[0]);
LOG_ERROR("loader response to OCL_PROBE 0x%08" PRIx32, dcc_buffer[0]);
return ERROR_FLASH_OPERATION_FAILED;
}
src/flash/nor/pic32mx.c
+2 -2
View File
@@ -608,7 +608,7 @@ static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
}
LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
" count: 0x%8.8" PRIx32, bank->base, offset, count);
if (offset & 0x3) {
LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
@@ -900,7 +900,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
if (timeout-- == 0) {
LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8, mchip_cmd);
break;
}
alive_sleep(1);
src/flash/nor/psoc4.c
+3 -3
View File
@@ -178,7 +178,7 @@ static const char *psoc4_decode_chip_protection(uint8_t protection)
case PSOC4_CHIP_PROT_KILL:
return "protection KILL";
default:
LOG_WARNING("Unknown protection state 0x%02" PRIx8 "", protection);
LOG_WARNING("Unknown protection state 0x%02" PRIx8, protection);
return "";
}
}
@@ -658,7 +658,7 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
memset(row_buffer + chunk_size, bank->default_padded_value, psoc4_info->row_size - chunk_size);
}
memcpy(row_buffer + row_offset, buffer, chunk_size);
LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32 "",
LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32,
offset, row_offset, chunk_size);
uint32_t macro_idx = row_num / PSOC4_ROWS_PER_MACRO;
@@ -858,7 +858,7 @@ static int get_psoc4_info(struct flash_bank *bank, struct command_invocation *cm
"/0x%02" PRIx16 ", silicon id 0x%08" PRIx32,
psoc4_info->family_id, family_id, silicon_id);
else {
command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32 "",
command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32,
family->name, silicon_id);
}
src/flash/nor/qn908x.c
+1 -1
View File
@@ -257,7 +257,7 @@ static int qn908x_update_reg(struct target *target, target_addr_t reg,
}
if (mask == 0xffffffff) {
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08"
PRIx32 "", reg, new_value);
PRIx32, reg, new_value);
} else {
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32
" -> 0x%.08" PRIx32, reg, orig_value, new_value);
src/flash/nor/stellaris.c
+12 -12
View File
@@ -573,13 +573,13 @@ static void stellaris_read_clock_info(struct flash_bank *bank)
unsigned long mainfreq;
target_read_u32(target, SCB_BASE | RCC, &rcc);
LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
LOG_DEBUG("Stellaris RCC %" PRIx32, rcc);
target_read_u32(target, SCB_BASE | RCC2, &rcc2);
LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
LOG_DEBUG("Stellaris RCC2 %" PRIx32, rcc);
target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
LOG_DEBUG("Stellaris PLLCFG %" PRIx32, pllcfg);
stellaris_info->rcc = rcc;
stellaris_info->rcc2 = rcc2;
@@ -659,7 +659,7 @@ static int stellaris_read_part_info(struct flash_bank *bank)
target_read_u32(target, SCB_BASE | DID1, &did1);
target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32,
did0, did1, stellaris_info->dc0, stellaris_info->dc1);
ver = DID0_VER(did0);
@@ -871,7 +871,7 @@ static int stellaris_erase(struct flash_bank *bank, unsigned int first,
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "",
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32,
banknr, flash_cris);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
@@ -967,7 +967,7 @@ static int stellaris_protect(struct flash_bank *bank, int set,
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32, flash_cris);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -1035,7 +1035,7 @@ static int stellaris_write_block(struct flash_bank *bank,
if (wcount * 4 < buf_min)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32,
bank, buffer, offset, wcount);
/* flash write code */
@@ -1115,7 +1115,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32,
bank, buffer, offset, count);
if (stellaris_info->did1 == 0)
@@ -1153,7 +1153,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
/* if an error occurred, we examine the reason, and quit */
target_read_u32(target, FLASH_CRIS, &flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32, flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
} else {
@@ -1165,7 +1165,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
while (words_remaining > 0) {
if (!(address & 0xff))
LOG_DEBUG("0x%" PRIx32 "", address);
LOG_DEBUG("0x%" PRIx32, address);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
@@ -1189,7 +1189,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
memcpy(last_word, buffer+bytes_written, bytes_remaining);
if (!(address & 0xff))
LOG_DEBUG("0x%" PRIx32 "", address);
LOG_DEBUG("0x%" PRIx32, address);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
@@ -1205,7 +1205,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
LOG_DEBUG("flash_cris 0x%" PRIx32, flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;
src/flash/nor/stm32f1x.c
+5 -5
View File
@@ -170,7 +170,7 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
retval = stm32x_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_BSY) == 0)
break;
if (timeout-- <= 0) {
@@ -825,7 +825,7 @@ static int stm32x_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
LOG_INFO("device id = 0x%08" PRIx32, dbgmcu_idcode);
uint16_t device_id = dbgmcu_idcode & 0xfff;
uint16_t rev_id = dbgmcu_idcode >> 16;
@@ -1444,8 +1444,8 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
if (optionbyte & (1 << OPT_ERROR))
command_print(CMD, "option byte complement error");
command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
command_print(CMD, "option byte register = 0x%" PRIx32, optionbyte);
command_print(CMD, "write protection register = 0x%" PRIx32, protection);
command_print(CMD, "read protection: %s",
(optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
@@ -1465,7 +1465,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
if (stm32x_info->has_dual_banks)
command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
command_print(CMD, "user data = 0x%02" PRIx16, user_data);
return ERROR_OK;
}
src/flash/nor/stm32l4x.c
+2 -2
View File
@@ -981,7 +981,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & stm32l4_info->sr_bsy_mask) == 0)
break;
if (timeout-- <= 0) {
@@ -2419,7 +2419,7 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command)
if (retval != ERROR_OK)
return retval;
command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32, reg_addr, value);
return retval;
}
src/flash/nor/stm32lx.c
+2 -2
View File
@@ -745,7 +745,7 @@ static int stm32lx_probe(struct flash_bank *bank)
stm32lx_info->idcode = device_id;
LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
LOG_DEBUG("device id = 0x%08" PRIx32, device_id);
for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
if ((device_id & 0xfff) == stm32lx_parts[n].id) {
@@ -1204,7 +1204,7 @@ static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int tim
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_SR__BSY) == 0)
break;
src/flash/nor/str7x.c
+1 -1
View File
@@ -335,7 +335,7 @@ static int str7x_erase(struct flash_bank *bank, unsigned int first,
for (unsigned int i = first; i <= last; i++)
sectors |= str7x_info->sector_bits[i];
LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
LOG_DEBUG("sectors: 0x%" PRIx32, sectors);
/* clear FLASH_ER register */
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
src/flash/nor/str9xpec.c
+1 -1
View File
@@ -735,7 +735,7 @@ COMMAND_HANDLER(str9xpec_handle_part_id_command)
idcode = buf_get_u32(buffer, 0, 32);
command_print(CMD, "str9xpec part id: 0x%8.8" PRIx32 "", idcode);
command_print(CMD, "str9xpec part id: 0x%8.8" PRIx32, idcode);
free(buffer);
src/flash/nor/tms470.c
+28 -28
View File
@@ -125,7 +125,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
/* read and parse the device identification register */
target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
LOG_INFO("device_ident_reg = 0x%08" PRIx32, device_ident_reg);
if ((device_ident_reg & 7) == 0) {
LOG_WARNING("Cannot identify target as a TMS470 family.");
@@ -300,7 +300,7 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command)
if (keys_set) {
command_print(CMD,
"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32,
flash_keys[0],
flash_keys[1],
flash_keys[2],
@@ -419,7 +419,7 @@ static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
*/
target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32, key_set[i]);
target_write_u32(target, 0xFFE89C0C, key_set[i]);
}
@@ -500,7 +500,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
fmmac2 &= ~0x0007;
fmmac2 |= (tms470_info->ordinal & 7);
target_write_u32(target, 0xFFE8BC04, fmmac2);
LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
LOG_DEBUG("set fmmac2 = 0x%04" PRIx32, fmmac2);
/*
* Disable level 1 sector protection by setting bit 15 of FMMAC1.
@@ -508,7 +508,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
target_read_u32(target, 0xFFE8BC00, &fmmac1);
fmmac1 |= 0x8000;
target_write_u32(target, 0xFFE8BC00, fmmac1);
LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
LOG_DEBUG("set fmmac1 = 0x%04" PRIx32, fmmac1);
/*
* FMTCREG = 0x2fc0;
@@ -542,7 +542,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
LOG_DEBUG("set fmptr3 = 0x9b64");
}
target_write_u32(target, 0xFFE8A080, fmmaxep);
LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
LOG_DEBUG("set fmmaxep = 0x%04" PRIx32, fmmaxep);
/*
* FMPTR4 = 0xa000
@@ -562,56 +562,56 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7));
delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
LOG_DEBUG("set fmpsetup = 0x%04" PRIx32, (delay << 4) | (delay << 8));
/*
* FMPVEVACCESS, based on delay.
*/
k = delay | (delay << 8);
target_write_u32(target, 0xFFE8A05C, k);
LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32, k);
/*
* FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
*/
k <<= 1;
target_write_u32(target, 0xFFE8A034, k);
LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpchold = 0x%04" PRIx32, k);
target_write_u32(target, 0xFFE8A040, k);
LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32, k);
target_write_u32(target, 0xFFE8A024, k);
LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32, k);
/*
* FMCVACCESS, based on delay.
*/
k = delay * 16;
target_write_u32(target, 0xFFE8A060, k);
LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32, k);
/*
* FMCSETUP, based on delay.
*/
k = 0x3000 | delay * 20;
target_write_u32(target, 0xFFE8A020, k);
LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmcsetup = 0x%04" PRIx32, k);
/*
* FMEHOLD, based on delay.
*/
k = (delay * 20) << 2;
target_write_u32(target, 0xFFE8A038, k);
LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmehold = 0x%04" PRIx32, k);
/*
* PWIDTH, CWIDTH, EWIDTH, based on delay.
*/
target_write_u32(target, 0xFFE8A050, delay * 8);
LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
LOG_DEBUG("set fmpwidth = 0x%04" PRIx32, delay * 8);
target_write_u32(target, 0xFFE8A058, delay * 1000);
LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
LOG_DEBUG("set fmcwidth = 0x%04" PRIx32, delay * 1000);
target_write_u32(target, 0xFFE8A054, delay * 5400);
LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
LOG_DEBUG("set fmewidth = 0x%04" PRIx32, delay * 5400);
return result;
}
@@ -625,7 +625,7 @@ static int tms470_flash_status(struct flash_bank *bank)
uint32_t fmmstat;
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
LOG_DEBUG("set fmmstat = 0x%04" PRIx32, fmmstat);
if (fmmstat & 0x0080) {
LOG_WARNING("tms470 flash command: erase still active after busy clear.");
@@ -680,7 +680,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
*/
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32, glbctrl | 0x10);
/* Force normal read mode. */
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
@@ -697,11 +697,11 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
if (sector < 16) {
target_read_u32(target, 0xFFE88008, &fmbsea);
target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
LOG_DEBUG("set fmbsea = 0x%04" PRIx32, fmbsea | (1 << sector));
} else {
target_read_u32(target, 0xFFE8800C, &fmbseb);
target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
LOG_DEBUG("set fmbseb = 0x%04" PRIx32, fmbseb | (1 << (sector - 16)));
}
bank->sectors[sector].is_protected = 0;
@@ -729,17 +729,17 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
if (sector < 16) {
target_write_u32(target, 0xFFE88008, fmbsea);
LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
LOG_DEBUG("set fmbsea = 0x%04" PRIx32, fmbsea);
bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
} else {
target_write_u32(target, 0xFFE8800C, fmbseb);
LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
LOG_DEBUG("set fmbseb = 0x%04" PRIx32, fmbseb);
bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
}
target_write_u32(target, 0xFFE89C00, orig_fmregopt);
LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
LOG_DEBUG("set fmregopt = 0x%08" PRIx32, orig_fmregopt);
target_write_u32(target, 0xFFFFFFDC, glbctrl);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32, glbctrl);
return result;
}
@@ -920,7 +920,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
if (word != 0xffff) {
LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
LOG_INFO("writing 0x%04x at 0x%08" PRIx32, word, addr);
/* clear status register */
target_write_u16(target, addr, 0x0040);
@@ -940,7 +940,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
} while (fmmstat & 0x0100);
if (fmmstat & 0x3ff) {
LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
LOG_ERROR("fmstat = 0x%04" PRIx32, fmmstat);
LOG_ERROR(
"Could not program word 0x%04x at address 0x%08" PRIx32 ".",
word,
@@ -949,7 +949,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
break;
}
} else
LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
LOG_INFO("skipping 0xffff at 0x%08" PRIx32, addr);
}
/* restore */
src/flash/nor/w600.c
+5 -5
View File
@@ -128,13 +128,13 @@ static int w600_start_do(struct flash_bank *bank, uint32_t cmd, uint32_t addr,
if (len > 0)
cmd |= QFLASH_CMD_DATALEN(len - 1) | QFLASH_CMD_DATA;
LOG_DEBUG("WRITE CMD: 0x%08" PRIx32 "", cmd);
LOG_DEBUG("WRITE CMD: 0x%08" PRIx32, cmd);
int retval = target_write_u32(target, QFLASH_CMD_INFO, cmd);
if (retval != ERROR_OK)
return retval;
addr |= QFLASH_START;
LOG_DEBUG("WRITE START: 0x%08" PRIx32 "", addr);
LOG_DEBUG("WRITE START: 0x%08" PRIx32, addr);
retval = target_write_u32(target, QFLASH_CMD_START, addr);
if (retval != ERROR_OK)
return retval;
@@ -148,7 +148,7 @@ static int w600_start_do(struct flash_bank *bank, uint32_t cmd, uint32_t addr,
LOG_DEBUG("READ START...");
retval = target_read_u32(target, QFLASH_CMD_START, &status);
if (retval == ERROR_OK)
LOG_DEBUG("READ START: 0x%08" PRIx32 "", status);
LOG_DEBUG("READ START: 0x%08" PRIx32, status);
else
LOG_DEBUG("READ START FAILED");
@@ -283,7 +283,7 @@ static int w600_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
LOG_INFO("flash_id id = 0x%08" PRIx32 "", flash_id);
LOG_INFO("flash_id id = 0x%08" PRIx32, flash_id);
w600_info->id = flash_id;
w600_info->param = NULL;
for (i = 0; i < ARRAY_SIZE(w600_param); i++) {
@@ -360,7 +360,7 @@ static int get_w600_info(struct flash_bank *bank, struct command_invocation *cmd
if (retval != ERROR_OK)
return retval;
command_print_sameline(cmd, "w600 : 0x%08" PRIx32 "", flash_id);
command_print_sameline(cmd, "w600 : 0x%08" PRIx32, flash_id);
return ERROR_OK;
}
src/jtag/drivers/jlink.c
+1 -1
View File
@@ -241,7 +241,7 @@ static void jlink_execute_scan(struct jtag_command *cmd)
static void jlink_execute_sleep(struct jtag_command *cmd)
{
LOG_DEBUG_IO("sleep %" PRIu32 "", cmd->cmd.sleep->us);
LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
jlink_flush();
jtag_sleep(cmd->cmd.sleep->us);
}
src/jtag/drivers/parport.c
+1 -1
View File
@@ -408,7 +408,7 @@ COMMAND_HANDLER(parport_handle_port_command)
}
}
command_print(CMD, "parport port = 0x%" PRIx16 "", parport_port);
command_print(CMD, "parport port = 0x%" PRIx16, parport_port);
return ERROR_OK;
}
src/jtag/drivers/xlnx-xvc.c
+1 -1
View File
@@ -424,7 +424,7 @@ out_err:
static void xlnx_xvc_execute_sleep(struct jtag_command *cmd)
{
LOG_DEBUG("sleep %" PRIu32 "", cmd->cmd.sleep->us);
LOG_DEBUG("sleep %" PRIu32, cmd->cmd.sleep->us);
usleep(cmd->cmd.sleep->us);
}
src/pld/xilinx_bit.c
+1 -1
View File
@@ -113,7 +113,7 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
return ERROR_PLD_FILE_LOAD_FAILED;
}
LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32, bit_file->source_file, bit_file->part_name,
bit_file->date, bit_file->time, bit_file->length);
fclose(input_file);
src/rtos/ecos.c
+2 -2
View File
@@ -1004,7 +1004,7 @@ static int ecos_update_threads(struct rtos *rtos)
if (tr_extra && reason_desc)
soff += snprintf(&eistr[soff], (eilen - soff), " (%s)", reason_desc);
if (pri_extra)
(void)snprintf(&eistr[soff], (eilen - soff), ", Priority: %" PRId64 "", priority);
(void)snprintf(&eistr[soff], (eilen - soff), ", Priority: %" PRId64, priority);
rtos->thread_details[tasks_found].extra_info_str = eistr;
rtos->thread_details[tasks_found].exists = true;
@@ -1073,7 +1073,7 @@ static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
param->uid_width,
(uint8_t *)&id);
if (retval != ERROR_OK) {
LOG_ERROR("Error reading unique id from eCos thread 0x%08" PRIX32 "", thread_index);
LOG_ERROR("Error reading unique id from eCos thread 0x%08" PRIX32, thread_index);
return retval;
}
src/server/gdb_server.c
+4 -4
View File
@@ -1557,7 +1557,7 @@ static int gdb_read_memory_packet(struct connection *connection,
buffer = malloc(len);
LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32, addr, len);
retval = ERROR_NOT_IMPLEMENTED;
if (target->rtos)
@@ -1629,7 +1629,7 @@ static int gdb_write_memory_packet(struct connection *connection,
buffer = malloc(len);
LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32, addr, len);
if (unhexify(buffer, separator, len) != len)
LOG_ERROR("unable to decode memory packet");
@@ -1705,7 +1705,7 @@ static int gdb_write_memory_binary_packet(struct connection *connection,
}
if (len) {
LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32, addr, len);
retval = ERROR_NOT_IMPLEMENTED;
if (target->rtos)
@@ -2874,7 +2874,7 @@ static int gdb_query_packet(struct connection *connection,
gdb_connection->output_flag = GDB_OUTPUT_NO;
if (retval == ERROR_OK) {
snprintf(gdb_reply, 10, "C%8.8" PRIx32 "", checksum);
snprintf(gdb_reply, 10, "C%8.8" PRIx32, checksum);
gdb_put_packet(connection, gdb_reply, 9);
} else {
retval = gdb_error(connection, retval);
src/target/arm11.c
+4 -4
View File
@@ -469,7 +469,7 @@ static int arm11_resume(struct target *target, bool current,
for (bp = target->breakpoints; bp; bp = bp->next) {
if (bp->address == address) {
LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
LOG_DEBUG("must step over %08" TARGET_PRIxADDR, bp->address);
arm11_step(target, true, 0, false);
break;
}
@@ -802,7 +802,7 @@ static int arm11_read_memory_inner(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32,
address,
size,
count);
@@ -900,7 +900,7 @@ static int arm11_write_memory_inner(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32,
address,
size,
count);
@@ -1264,7 +1264,7 @@ COMMAND_HANDLER(arm11_handle_vcr)
return ERROR_COMMAND_SYNTAX_ERROR;
}
LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
LOG_INFO("VCR 0x%08" PRIx32, arm11->vcr);
return ERROR_OK;
}
src/target/arm720t.c
+1 -1
View File
@@ -197,7 +197,7 @@ static int arm720t_post_debug_entry(struct target *target)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
src/target/arm7_9_common.c
+9 -9
View File
@@ -643,7 +643,7 @@ int arm7_9_execute_sys_speed(struct target *target)
keep_alive();
}
if (timeout) {
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "",
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32,
buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
return ERROR_TARGET_TIMEOUT;
}
@@ -1332,7 +1332,7 @@ static int arm7_9_debug_entry(struct target *target)
for (i = 0; i <= 15; i++) {
struct reg *r = arm_reg_current(arm, i);
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
LOG_DEBUG("r%i: 0x%8.8" PRIx32, i, context[i]);
buf_set_u32(r->value, 0, 32, context[i]);
/* r0 and r15 (pc) have to be restored later */
@@ -1340,7 +1340,7 @@ static int arm7_9_debug_entry(struct target *target)
r->valid = true;
}
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
LOG_DEBUG("entered debug state at PC 0x%" PRIx32, context[15]);
/* exceptions other than USR & SYS have a saved program status register */
if (arm->spsr) {
@@ -1594,7 +1594,7 @@ static int arm7_9_restore_context(struct target *target)
struct arm_reg *reg_arch_info;
reg_arch_info = reg->arch_info;
if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) {
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "",
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32,
i,
buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
@@ -1744,7 +1744,7 @@ int arm7_9_resume(struct target *target,
uint32_t current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
return retval;
}
@@ -1789,7 +1789,7 @@ int arm7_9_resume(struct target *target,
LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR, breakpoint->address);
retval = arm7_9_set_breakpoint(target, breakpoint);
if (retval != ERROR_OK)
return retval;
@@ -1937,7 +1937,7 @@ int arm7_9_step(struct target *target, bool current, target_addr_t address,
uint32_t current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
return retval;
}
@@ -2116,7 +2116,7 @@ int arm7_9_read_memory(struct target *target,
int retval;
int last_reg = 0;
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
if (target->state != TARGET_HALTED) {
@@ -2636,7 +2636,7 @@ int arm7_9_bulk_write_memory(struct target *target,
uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
if (endaddress != (address + count*4)) {
LOG_ERROR(
"DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "",
"DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32,
(address + count*4),
endaddress);
retval = ERROR_FAIL;
src/target/arm926ejs.c
+2 -2
View File
@@ -427,7 +427,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm926ejs->cp15_control_reg);
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) {
uint32_t cache_type_reg;
@@ -458,7 +458,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32,
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
uint32_t cache_dbg_ctrl;
src/target/arm_disassembler.c
+6 -6
View File
@@ -324,7 +324,7 @@ static int evaluate_blx_imm(uint32_t opcode,
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "",
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32,
address,
opcode,
target_address);
@@ -596,7 +596,7 @@ static int evaluate_load_store(uint32_t opcode,
if (!i) { /* #+-<offset_12> */
uint32_t offset_12 = (opcode & 0xfff);
if (offset_12)
snprintf(offset, 32, ", #%s0x%" PRIx32 "", (u) ? "" : "-", offset_12);
snprintf(offset, 32, ", #%s0x%" PRIx32, (u) ? "" : "-", offset_12);
else
snprintf(offset, 32, "%s", "");
@@ -1079,7 +1079,7 @@ static int evaluate_misc_load_store(uint32_t opcode,
if (i) {/* Immediate offset/index (#+-<offset_8>)*/
uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
snprintf(offset, 32, "#%s0x%" PRIx32 "", (u) ? "" : "-", offset_8);
snprintf(offset, 32, "#%s0x%" PRIx32, (u) ? "" : "-", offset_8);
instruction->info.load_store.offset_mode = 0;
instruction->info.load_store.offset.offset = offset_8;
@@ -1546,7 +1546,7 @@ static int evaluate_misc_instr(uint32_t opcode,
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32,
address,
opcode,
mnemonic,
@@ -1790,7 +1790,7 @@ static int evaluate_data_proc(uint32_t opcode,
immediate = ror(immed_8, rotate_imm * 2);
snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);
snprintf(shifter_operand, 32, "#0x%" PRIx32, immediate);
instruction->info.data_proc.variant = 0;
instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
@@ -2628,7 +2628,7 @@ static int evaluate_breakpoint_thumb(uint16_t opcode,
instruction->type = ARM_BKPT;
snprintf(instruction->text, 128,
"0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t%#2.2" PRIx32 "",
"0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t%#2.2" PRIx32,
address, opcode, imm);
return ERROR_OK;
src/target/armv4_5.c
+1 -1
View File
@@ -1564,7 +1564,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).value, 0, 32);
if (regvalue != context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).name, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
src/target/armv4_5_mmu.c
+2 -2
View File
@@ -31,7 +31,7 @@ int armv4_5_mmu_translate_va(struct target *target,
return retval;
first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8" PRIx32, first_lvl_descriptor);
if ((first_lvl_descriptor & 0x3) == 0) {
LOG_ERROR("Address translation failure");
@@ -68,7 +68,7 @@ int armv4_5_mmu_translate_va(struct target *target,
second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32, second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 0) {
LOG_ERROR("Address translation failure");
src/target/avr32_ap7k.c
+7 -7
View File
@@ -117,7 +117,7 @@ static int avr32_write_core_reg(struct target *target, int num)
reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32);
ap7k->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, reg_value);
ap7k->core_cache->reg_list[num].valid = true;
ap7k->core_cache->reg_list[num].dirty = false;
@@ -337,7 +337,7 @@ static int avr32_ap7k_resume(struct target *target, bool current,
/* Single step past breakpoint at current address */
breakpoint = breakpoint_find(target, resume_pc);
if (breakpoint) {
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR, breakpoint->address);
#if 0
avr32_ap7k_unset_breakpoint(target, breakpoint);
avr32_ap7k_single_step_core(target);
@@ -372,11 +372,11 @@ static int avr32_ap7k_resume(struct target *target, bool current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
return ERROR_OK;
@@ -425,7 +425,7 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address,
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address,
size,
count);
@@ -465,7 +465,7 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address,
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address,
size,
count);
@@ -548,7 +548,7 @@ static int avr32_ap7k_arch_state(struct target *target)
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32,
debug_reason_name(target), ap7k->jtag.dpc);
return ERROR_OK;
src/target/cortex_m.c
+4 -4
View File
@@ -554,7 +554,7 @@ static int cortex_m_clear_halt(struct target *target)
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32, cortex_m->nvic_dfsr);
return ERROR_OK;
}
@@ -616,7 +616,7 @@ static int cortex_m_endreset_event(struct target *target)
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32, dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
@@ -1911,7 +1911,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
comparator_list[fp_num].fpcr_value = fpcr_value;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32,
fp_num,
comparator_list[fp_num].fpcr_value);
if (!cortex_m->fpb_enabled) {
@@ -2773,7 +2773,7 @@ int cortex_m_examine(struct target *target)
else
LOG_TARGET_INFO(target, "The erratum 3092511 workaround will resume after an incorrect halt");
}
LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32, cpuid);
if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
uint32_t mvfr0;
src/target/dsp563xx.c
+2 -2
View File
@@ -1517,7 +1517,7 @@ static int dsp563xx_read_memory_core(struct target *target,
uint8_t *b;
LOG_DEBUG(
"memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
"memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
mem_type,
address,
size,
@@ -1698,7 +1698,7 @@ static int dsp563xx_write_memory_core(struct target *target,
const uint8_t *b;
LOG_DEBUG(
"memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
"memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
mem_type,
address,
size,
src/target/embeddedice.c
+1 -1
View File
@@ -502,7 +502,7 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
LOG_DEBUG("%i: 0x%8.8" PRIx32, ice_reg->addr, value);
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
src/target/etb.c
+1 -1
View File
@@ -287,7 +287,7 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
uint8_t reg_addr = etb_reg->addr & 0x7f;
struct scan_field fields[3];
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
LOG_DEBUG("%i: 0x%8.8" PRIx32, (int)(etb_reg->addr), value);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);
src/target/etm.c
+5 -5
View File
@@ -584,7 +584,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
return ERROR_COMMAND_SYNTAX_ERROR;
}
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32, r->name, reg_addr, value);
retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
if (retval != ERROR_OK)
@@ -986,7 +986,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
command_print(cmd, "data abort");
else {
command_print(cmd,
"exception vector 0x%2.2" PRIx32 "",
"exception vector 0x%2.2" PRIx32,
ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
@@ -1044,7 +1044,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
if (ctx->ptr_ok)
command_print(cmd,
"address: 0x%8.8" PRIx32 "",
"address: 0x%8.8" PRIx32,
ctx->last_ptr);
}
@@ -1059,7 +1059,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
if (etmv1_data(ctx, 4, &data) != 0)
return ERROR_ETM_ANALYSIS_FAILED;
command_print(cmd,
"data: 0x%8.8" PRIx32 "",
"data: 0x%8.8" PRIx32,
data);
}
}
@@ -1069,7 +1069,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
if (etmv1_data(ctx, arm_access_size(&instruction),
&data) != 0)
return ERROR_ETM_ANALYSIS_FAILED;
command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
command_print(cmd, "data: 0x%8.8" PRIx32, data);
}
}
src/target/feroceon.c
+1 -1
View File
@@ -555,7 +555,7 @@ static int feroceon_bulk_write_memory(struct target *target,
if (endaddress != address + count*4) {
LOG_ERROR("DCC write failed,"
" expected end address 0x%08" TARGET_PRIxADDR
" got 0x%0" PRIx32 "",
" got 0x%0" PRIx32,
address + count*4, endaddress);
retval = ERROR_FAIL;
}
src/target/image.c
+3 -3
View File
@@ -670,7 +670,7 @@ static int image_elf32_read_section(struct image *image,
if (offset < field32(elf, segment->p_filesz)) {
/* maximal size present in file for the current segment */
read_size = MIN(size, field32(elf, segment->p_filesz) - offset);
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR, read_size,
field32(elf, segment->p_offset) + offset);
/* read initialized area of the segment */
retval = fileio_seek(elf->fileio, field32(elf, segment->p_offset) + offset);
@@ -713,7 +713,7 @@ static int image_elf64_read_section(struct image *image,
if (offset < field64(elf, segment->p_filesz)) {
/* maximal size present in file for the current segment */
read_size = MIN(size, field64(elf, segment->p_filesz) - offset);
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR, read_size,
field64(elf, segment->p_offset) + offset);
/* read initialized area of the segment */
retval = fileio_seek(elf->fileio, field64(elf, segment->p_offset) + offset);
@@ -1088,7 +1088,7 @@ int image_read_section(struct image *image,
/* don't read past the end of a section */
if (offset + size > image->sections[section].size) {
LOG_DEBUG(
"read past end of section: 0x%8.8" TARGET_PRIxADDR " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32 "",
"read past end of section: 0x%8.8" TARGET_PRIxADDR " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32,
offset,
size,
image->sections[section].size);
src/target/mips32.c
+3 -3
View File
@@ -374,7 +374,7 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
LOG_DEBUG("read core reg %i value 0x%" PRIx64, num, reg_value);
return ERROR_OK;
}
@@ -419,7 +419,7 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
mips32->core_regs.gpr[cnum] = (uint32_t)reg_value;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
@@ -485,7 +485,7 @@ int mips32_arch_state(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32,
mips_isa_strings[mips32->isa_mode],
debug_reason_name(target),
buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
src/target/mips64.c
+2 -2
View File
@@ -283,7 +283,7 @@ static int mips64_write_core_reg(struct target *target, int num)
reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
mips64->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
mips64->core_cache->reg_list[num].valid = true;
mips64->core_cache->reg_list[num].dirty = false;
@@ -361,7 +361,7 @@ int mips64_arch_state(struct target *target)
exit(-1);
}
LOG_USER("target halted due to %s, pc: 0x%" PRIx64 "",
LOG_USER("target halted due to %s, pc: 0x%" PRIx64,
debug_reason_name(target), buf_get_u64(pc->value, 0, 64));
return ERROR_OK;
src/target/mips_ejtag.c
+1 -1
View File
@@ -245,7 +245,7 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
/* break bit will be cleared by hardware */
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32, ejtag_ctrl);
if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
goto error;
src/target/mips_m4k.c
+8 -8
View File
@@ -486,11 +486,11 @@ static int mips_m4k_internal_restore(struct target *target, bool current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
return ERROR_OK;
@@ -638,7 +638,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
ejtag_info->ejtag_ibm_offs, 0x00000000);
target_write_u32(target, comparator_list[bp_num].reg_address +
ejtag_info->ejtag_ibc_offs, 1);
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32,
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
} else if (breakpoint->type == BKPT_SOFT) {
@@ -928,7 +928,7 @@ static int mips_m4k_set_watchpoint(struct target *target,
/* TODO: probably this value is ignored on 2.0 */
target_write_u32(target, comparator_list[wp_num].reg_address +
ejtag_info->ejtag_dbv_offs, 0);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32, wp_num, comparator_list[wp_num].bp_value);
return ERROR_OK;
}
@@ -1012,7 +1012,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address,
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
if (target->state != TARGET_HALTED) {
@@ -1077,7 +1077,7 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address,
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
if (target->state != TARGET_HALTED) {
@@ -1204,7 +1204,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
int retval;
int write_t = 1;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32,
address, count);
/* check alignment */
@@ -1270,7 +1270,7 @@ static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t addres
int retval;
int write_t = 0;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32,
address, count);
/* check alignment */
src/target/mips_mips64.c
+7 -7
View File
@@ -473,7 +473,7 @@ static int mips_mips64_set_watchpoint(struct target *target,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx64 "", wp_num, c->bp_value);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx64, wp_num, c->bp_value);
return ERROR_OK;
}
@@ -642,7 +642,7 @@ static int mips_mips64_resume(struct target *target, bool current,
/* Single step past breakpoint at current address */
bp = breakpoint_find(target, (uint64_t) resume_pc);
if (bp) {
LOG_DEBUG("unset breakpoint at 0x%16.16" PRIx64 "",
LOG_DEBUG("unset breakpoint at 0x%16.16" PRIx64,
bp->address);
retval = mips_mips64_unset_breakpoint(target, bp);
if (retval != ERROR_OK)
@@ -682,7 +682,7 @@ static int mips_mips64_resume(struct target *target, bool current,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("target resumed at 0x%" PRIx64 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx64, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
retval = target_call_event_callbacks(target,
@@ -690,7 +690,7 @@ static int mips_mips64_resume(struct target *target, bool current,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("target debug resumed at 0x%" PRIx64 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx64, resume_pc);
}
return ERROR_OK;
@@ -911,7 +911,7 @@ static int mips_mips64_read_memory(struct target *target, uint64_t address,
} else
t = buffer;
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
retval = mips64_pracc_read_mem(ejtag_info, address, size, count,
(void *)t);
@@ -949,7 +949,7 @@ static int mips_mips64_bulk_write_memory(struct target *target,
struct working_area *fast_data_area;
int retval;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32,
address, count);
if (address & 0x7)
@@ -1066,7 +1066,7 @@ static int mips_mips64_write_memory(struct target *target, uint64_t address,
buffer = t;
}
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
retval = mips64_pracc_write_mem(ejtag_info, address, size, count,
src/target/stm8.c
+7 -7
View File
@@ -1094,11 +1094,11 @@ static int stm8_resume(struct target *target, bool current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
return ERROR_OK;
@@ -1173,7 +1173,7 @@ static int stm8_read_core_reg(struct target *target, unsigned int num)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = stm8->core_regs[num];
LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num, reg_value);
LOG_DEBUG("read core reg %i value 0x%" PRIx32, num, reg_value);
buf_set_u32(stm8->core_cache->reg_list[num].value, 0, 32, reg_value);
stm8->core_cache->reg_list[num].valid = true;
stm8->core_cache->reg_list[num].dirty = false;
@@ -1193,7 +1193,7 @@ static int stm8_write_core_reg(struct target *target, unsigned int num)
reg_value = buf_get_u32(stm8->core_cache->reg_list[num].value, 0, 32);
stm8->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, reg_value);
stm8->core_cache->reg_list[num].valid = true;
stm8->core_cache->reg_list[num].dirty = false;
@@ -1327,7 +1327,7 @@ static int stm8_arch_state(struct target *target)
{
struct stm8_common *stm8 = target_to_stm8(target);
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32,
debug_reason_name(target),
buf_get_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32));
@@ -1438,7 +1438,7 @@ static int stm8_set_breakpoint(struct target *target,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32,
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
} else if (breakpoint->type == BKPT_SOFT) {
@@ -1626,7 +1626,7 @@ static int stm8_set_watchpoint(struct target *target,
watchpoint_set(watchpoint, wp_num);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32,
wp_num,
comparator_list[wp_num].bp_value);
src/target/target.c
+8 -8
View File
@@ -2544,7 +2544,7 @@ int target_read_u64(struct target *target, target_addr_t address, uint64_t *valu
if (retval == ERROR_OK) {
*value = target_buffer_get_u64(target, value_buf);
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64,
address,
*value);
} else {
@@ -2568,7 +2568,7 @@ int target_read_u32(struct target *target, target_addr_t address, uint32_t *valu
if (retval == ERROR_OK) {
*value = target_buffer_get_u32(target, value_buf);
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32,
address,
*value);
} else {
@@ -2635,7 +2635,7 @@ int target_write_u64(struct target *target, target_addr_t address, uint64_t valu
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64,
address,
value);
@@ -2656,7 +2656,7 @@ int target_write_u32(struct target *target, target_addr_t address, uint32_t valu
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32,
address,
value);
@@ -2716,7 +2716,7 @@ int target_write_phys_u64(struct target *target, target_addr_t address, uint64_t
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64,
address,
value);
@@ -2737,7 +2737,7 @@ int target_write_phys_u32(struct target *target, target_addr_t address, uint32_t
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32,
address,
value);
@@ -3973,7 +3973,7 @@ static int handle_bp_command_set(struct command_invocation *cmd,
retval = context_breakpoint_add(target, asid, length, hw);
/* error is always logged in context_breakpoint_add(), do not print it again */
if (retval == ERROR_OK)
command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32 "", asid);
command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32, asid);
} else {
if (!target->type->add_hybrid_breakpoint) {
@@ -3983,7 +3983,7 @@ static int handle_bp_command_set(struct command_invocation *cmd,
retval = hybrid_breakpoint_add(target, addr, asid, length, hw);
/* error is always logged in hybrid_breakpoint_add(), do not print it again */
if (retval == ERROR_OK)
command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid);
command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32, asid);
}
return retval;
}
src/target/trace.c
+1 -1
View File
@@ -115,7 +115,7 @@ COMMAND_HANDLER(handle_trace_history_command)
if (trace->trace_history[i % trace->trace_history_size] < trace->num_trace_points) {
uint32_t address;
address = trace->trace_points[trace->trace_history[i % trace->trace_history_size]].address;
command_print(CMD, "trace point %i: 0x%8.8" PRIx32 "",
command_print(CMD, "trace point %i: 0x%8.8" PRIx32,
(int)(trace->trace_history[i % trace->trace_history_size]),
address);
} else
src/target/x86_32_common.c
+3 -3
View File
@@ -1027,7 +1027,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
if (read_phys_mem(t, physaddr, 1, 1, bp->orig_instr))
return ERROR_FAIL;
LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8 "", *bp->orig_instr);
LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8, *bp->orig_instr);
/* just write the instruction trap byte */
if (write_phys_mem(t, physaddr, 1, 1, &opcode))
@@ -1040,7 +1040,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
if (readback != SW_BP_OPCODE) {
LOG_ERROR("%s software breakpoint error at " TARGET_ADDR_FMT ", check memory",
__func__, bp->address);
LOG_ERROR("%s readback=0x%02" PRIx8 " orig=0x%02" PRIx8 "",
LOG_ERROR("%s readback=0x%02" PRIx8 " orig=0x%02" PRIx8,
__func__, readback, *bp->orig_instr);
return ERROR_FAIL;
}
@@ -1089,7 +1089,7 @@ static int unset_swbp(struct target *t, struct breakpoint *bp)
} else {
LOG_ERROR("%s software breakpoint remove error at " TARGET_ADDR_FMT ", check memory",
__func__, bp->address);
LOG_ERROR("%s current=0x%02" PRIx8 " orig=0x%02" PRIx8 "",
LOG_ERROR("%s current=0x%02" PRIx8 " orig=0x%02" PRIx8,
__func__, current_instr, *bp->orig_instr);
return ERROR_FAIL;
}
src/target/xscale.c
+11 -11
View File
@@ -640,7 +640,7 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
int word;
struct scan_field fields[2];
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32, va);
/* LDIC into IR */
xscale_jtag_set_instr(target->tap,
@@ -856,24 +856,24 @@ static int xscale_debug_entry(struct target *target)
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
arm->core_cache->reg_list[0].dirty = true;
arm->core_cache->reg_list[0].valid = true;
LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
LOG_DEBUG("r0: 0x%8.8" PRIx32, buffer[0]);
/* move pc from buffer to register cache */
buf_set_u32(arm->pc->value, 0, 32, buffer[1]);
arm->pc->dirty = true;
arm->pc->valid = true;
LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
LOG_DEBUG("pc: 0x%8.8" PRIx32, buffer[1]);
/* move data from buffer to register cache */
for (i = 1; i <= 7; i++) {
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
arm->core_cache->reg_list[i].dirty = true;
arm->core_cache->reg_list[i].valid = true;
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
LOG_DEBUG("r%i: 0x%8.8" PRIx32, i, buffer[i + 1]);
}
arm_set_cpsr(arm, buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32, buffer[9]);
if (!is_arm_mode(arm->core_mode)) {
target->state = TARGET_UNKNOWN;
@@ -1159,7 +1159,7 @@ static int xscale_resume(struct target *target, bool current,
uint32_t current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
}
@@ -1184,7 +1184,7 @@ static int xscale_resume(struct target *target, bool current,
/* send register */
xscale_send_u32(target,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32,
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
@@ -1248,7 +1248,7 @@ static int xscale_resume(struct target *target, bool current,
for (i = 7; i >= 0; i--) {
/* send register */
xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32,
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
@@ -1293,7 +1293,7 @@ static int xscale_step_inner(struct target *target, bool current,
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
return retval;
}
@@ -1337,7 +1337,7 @@ static int xscale_step_inner(struct target *target, bool current,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32, i,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
@@ -3557,7 +3557,7 @@ COMMAND_HANDLER(xscale_handle_cp15)
/* read cp15 control register */
xscale_get_reg(reg);
value = buf_get_u32(reg->value, 0, 32);
command_print(CMD, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
command_print(CMD, "%s (/%i): 0x%" PRIx32, reg->name, (int)(reg->size),
value);
} else if (CMD_ARGC == 2) {
uint32_t value;