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openocd: drop empty string suffix from format strings

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Format strings are often split to allow using the conversion
specifiers macros from <inttypes.h>.
When the format string ends with one of such macros, there is no
need to add an empty string "" after the macro.

In current code we have 203 cases of empty string present, against
1159 cases of string ending with the macro.

Uniform the style across OpenOCD by removing the empty string.

Don't modify the files 'angie.c' and 'max32xxx.c' as they are
already changed by other independent commits.

Change-Id: I23f1120101ce1da67c6578635fc6507a58c803e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9065
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2025-08-01 17:06:05 +02:00
parent 9fe3780432
commit 003cb92cd5
52 changed files with 200 additions and 200 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/flash/nor/at91sam7.c
View File

@@ -291,14 +291,14 @@ static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t wait
while ((!((status = at91sam7_get_flash_status(bank->target,
bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
LOG_DEBUG("status[%i]: 0x%" PRIx32, (int)bank->bank_number, status);
alive_sleep(1);
}
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
LOG_DEBUG("status[%i]: 0x%" PRIx32, bank->bank_number, status);
if (status & 0x0C) {
LOG_ERROR("status register: 0x%" PRIx32 "", status);
LOG_ERROR("status register: 0x%" PRIx32, status);
if (status & 0x4)
LOG_ERROR("Lock Error Bit Detected, Operation Abort");
if (status & 0x8)
@@ -915,7 +915,7 @@ static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32
dst_min_alignment = at91sam7_info->pagesize;
if (offset % dst_min_alignment) {
LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32,
offset,
dst_min_alignment);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;

2
src/flash/nor/atsamv.c
View File

@@ -310,7 +310,7 @@ static int samv_probe(struct flash_bank *bank)
int r = samv_get_device_id(bank, &device_id);
if (r != ERROR_OK)
return r;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
LOG_INFO("device id = 0x%08" PRIx32, device_id);
uint8_t eproc = (device_id >> 5) & 0x7;
if (eproc != 0) {

14
src/flash/nor/avrf.c
View File

@@ -126,7 +126,7 @@ static int avr_jtagprg_chiperase(struct avr_common *avr)
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
LOG_DEBUG("poll_value = 0x%04" PRIx32, poll_value);
} while (!(poll_value & 0x0200));
return ERROR_OK;
@@ -187,7 +187,7 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr,
AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
LOG_DEBUG("poll_value = 0x%04" PRIx32, poll_value);
} while (!(poll_value & 0x0200));
return ERROR_OK;
@@ -253,8 +253,8 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
LOG_DEBUG("count is %" PRIu32 "", count);
LOG_DEBUG("offset is 0x%08" PRIx32, offset);
LOG_DEBUG("count is %" PRIu32, count);
if (avr_jtagprg_enterprogmode(avr) != ERROR_OK)
return ERROR_FAIL;
@@ -308,7 +308,7 @@ static int avrf_probe(struct flash_bank *bank)
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
LOG_INFO("device id = 0x%08" PRIx32, device_id);
if (EXTRACT_MFG(device_id) != 0x1F)
LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
EXTRACT_MFG(device_id),
@@ -373,7 +373,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
if (mcu_execute_queue() != ERROR_OK)
return ERROR_FAIL;
LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
LOG_INFO("device id = 0x%08" PRIx32, device_id);
if (EXTRACT_MFG(device_id) != 0x1F)
LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
EXTRACT_MFG(device_id),
@@ -390,7 +390,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
if (avr_info) {
/* chip found */
command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32 "", avr_info->name,
command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32, avr_info->name,
EXTRACT_VER(device_id));
return ERROR_OK;
} else {

4
src/flash/nor/cfi.c
View File

@@ -2722,7 +2722,7 @@ int cfi_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG(
"erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
"erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32,
i,
(cfi_info->erase_region_info[i] & 0xffff) + 1,
(cfi_info->erase_region_info[i] >> 16) * 256);
@@ -2849,7 +2849,7 @@ int cfi_probe(struct flash_bank *bank)
}
if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width)) {
LOG_WARNING(
"CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "",
"CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32,
(cfi_info->dev_size * bank->bus_width / bank->chip_width),
offset);
}

2
src/flash/nor/efm32.c
View File

@@ -430,7 +430,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout,
if (ret != ERROR_OK)
break;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if (((status & wait_mask) == 0) && (wait_for_set == 0))
break;

2
src/flash/nor/em357.c
View File

@@ -115,7 +115,7 @@ static int em357_wait_status_busy(struct flash_bank *bank, int timeout)
retval = em357_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_BSY) == 0)
break;
if (timeout-- <= 0) {

4
src/flash/nor/lpc288x.c
View File

@@ -279,7 +279,7 @@ static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
/* all writes must start on a sector boundary... */
if (offset % bank->sectors[i].size) {
LOG_INFO(
"offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
"offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32,
offset,
bank->sectors[i].size);
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
@@ -293,7 +293,7 @@ static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
/* Range check... */
if (first_sector == 0xffffffff || last_sector == 0xffffffff) {
LOG_INFO("Range check failed %" PRIx32 " %" PRIx32 "", offset, count);
LOG_INFO("Range check failed %" PRIx32 " %" PRIx32, offset, count);
return ERROR_FLASH_DST_OUT_OF_BANK;
}

2
src/flash/nor/mspm0.c
View File

@@ -429,7 +429,7 @@ static int mspm0_read_part_info(struct flash_bank *bank)
LOG_WARNING("Unknown Device ID[0x%" PRIx32 "], cannot identify target",
did);
LOG_DEBUG("did 0x%" PRIx32 ", traceid 0x%" PRIx32 ", userid 0x%" PRIx32
", flashram 0x%" PRIx32 "", did, mspm0_info->traceid, userid,
", flashram 0x%" PRIx32, did, mspm0_info->traceid, userid,
flashram);
return ERROR_FLASH_OPERATION_FAILED;
}

10
src/flash/nor/numicro.c
View File

@@ -567,7 +567,7 @@ static int numicro_reg_unlock(struct target *target)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected);
LOG_DEBUG("protected = 0x%08" PRIx32, is_protected);
if (is_protected == 0) { /* means protected - so unlock it */
/* unlock flash registers */
retval = target_write_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, REG_KEY1);
@@ -828,7 +828,7 @@ static int numicro_protect_check(struct flash_bank *bank)
numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0 - m_address_bias_offset, 0, &config[0]);
numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1 - m_address_bias_offset, 0, &config[1]);
LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]);
LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32, config[0], config[1]);
if ((config[0] & (1<<7)) == 0)
LOG_INFO("CBS=0: Boot From LPROM");
@@ -908,7 +908,7 @@ static int numicro_erase(struct flash_bank *bank, unsigned int first,
if (retval != ERROR_OK)
return retval;
if ((status & ISPCON_ISPFF) != 0) {
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
LOG_DEBUG("failure: 0x%" PRIx32, status);
/* if bit is set, then must write to it to clear it. */
retval = target_write_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, (status | ISPCON_ISPFF));
if (retval != ERROR_OK)
@@ -1007,7 +1007,7 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
return retval;
if ((status & ISPCON_ISPFF) != 0) {
LOG_DEBUG("failure: 0x%" PRIx32 "", status);
LOG_DEBUG("failure: 0x%" PRIx32, status);
/* if bit is set, then must write to it to clear it. */
retval = target_write_u32(target,
NUMICRO_FLASH_ISPCON - m_address_bias_offset,
@@ -1037,7 +1037,7 @@ static int numicro_get_cpu_type(struct target *target, const struct numicro_cpu_
return ERROR_FLASH_OPERATION_FAILED;
}
LOG_INFO("Device ID: 0x%08" PRIx32 "", part_id);
LOG_INFO("Device ID: 0x%08" PRIx32, part_id);
/* search part numbers */
for (size_t i = 0; i < ARRAY_SIZE(numicro_parts); i++) {
if (part_id == numicro_parts[i].partid) {

8
src/flash/nor/ocl.c
View File

@@ -82,9 +82,9 @@ static int ocl_erase(struct flash_bank *bank, unsigned int first,
if (dcc_buffer[1] != OCL_CMD_DONE) {
if (dcc_buffer[0] == OCL_ERASE_ALL)
LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08" PRIx32 "", dcc_buffer[1]);
LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08" PRIx32, dcc_buffer[1]);
else
LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08" PRIx32 "", dcc_buffer[1]);
LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08" PRIx32, dcc_buffer[1]);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -178,7 +178,7 @@ static int ocl_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
}
if (dcc_buffer[0] != OCL_CMD_DONE) {
LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08" PRIx32 "", dcc_buffer[0]);
LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08" PRIx32, dcc_buffer[0]);
free(dcc_buffer);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -217,7 +217,7 @@ static int ocl_probe(struct flash_bank *bank)
return retval;
if (dcc_buffer[0] != OCL_CMD_DONE) {
LOG_ERROR("loader response to OCL_PROBE 0x%08" PRIx32 "", dcc_buffer[0]);
LOG_ERROR("loader response to OCL_PROBE 0x%08" PRIx32, dcc_buffer[0]);
return ERROR_FLASH_OPERATION_FAILED;
}

4
src/flash/nor/pic32mx.c
View File

@@ -608,7 +608,7 @@ static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
}
LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
" count: 0x%8.8" PRIx32, bank->base, offset, count);
if (offset & 0x3) {
LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
@@ -900,7 +900,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
mchip_cmd = MCHP_STATUS;
mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
if (timeout-- == 0) {
LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8, mchip_cmd);
break;
}
alive_sleep(1);

6
src/flash/nor/psoc4.c
View File

@@ -178,7 +178,7 @@ static const char *psoc4_decode_chip_protection(uint8_t protection)
case PSOC4_CHIP_PROT_KILL:
return "protection KILL";
default:
LOG_WARNING("Unknown protection state 0x%02" PRIx8 "", protection);
LOG_WARNING("Unknown protection state 0x%02" PRIx8, protection);
return "";
}
}
@@ -658,7 +658,7 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
memset(row_buffer + chunk_size, bank->default_padded_value, psoc4_info->row_size - chunk_size);
}
memcpy(row_buffer + row_offset, buffer, chunk_size);
LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32 "",
LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32,
offset, row_offset, chunk_size);
uint32_t macro_idx = row_num / PSOC4_ROWS_PER_MACRO;
@@ -858,7 +858,7 @@ static int get_psoc4_info(struct flash_bank *bank, struct command_invocation *cm
"/0x%02" PRIx16 ", silicon id 0x%08" PRIx32,
psoc4_info->family_id, family_id, silicon_id);
else {
command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32 "",
command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32,
family->name, silicon_id);
}

2
src/flash/nor/qn908x.c
View File

@@ -257,7 +257,7 @@ static int qn908x_update_reg(struct target *target, target_addr_t reg,
}
if (mask == 0xffffffff) {
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08"
PRIx32 "", reg, new_value);
PRIx32, reg, new_value);
} else {
LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32
" -> 0x%.08" PRIx32, reg, orig_value, new_value);

24
src/flash/nor/stellaris.c
View File

@@ -573,13 +573,13 @@ static void stellaris_read_clock_info(struct flash_bank *bank)
unsigned long mainfreq;
target_read_u32(target, SCB_BASE | RCC, &rcc);
LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
LOG_DEBUG("Stellaris RCC %" PRIx32, rcc);
target_read_u32(target, SCB_BASE | RCC2, &rcc2);
LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
LOG_DEBUG("Stellaris RCC2 %" PRIx32, rcc);
target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
LOG_DEBUG("Stellaris PLLCFG %" PRIx32, pllcfg);
stellaris_info->rcc = rcc;
stellaris_info->rcc2 = rcc2;
@@ -659,7 +659,7 @@ static int stellaris_read_part_info(struct flash_bank *bank)
target_read_u32(target, SCB_BASE | DID1, &did1);
target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32,
did0, did1, stellaris_info->dc0, stellaris_info->dc1);
ver = DID0_VER(did0);
@@ -871,7 +871,7 @@ static int stellaris_erase(struct flash_bank *bank, unsigned int first,
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32 "",
LOG_WARNING("Error erasing flash page %i, flash_cris 0x%" PRIx32,
banknr, flash_cris);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
@@ -967,7 +967,7 @@ static int stellaris_protect(struct flash_bank *bank, int set,
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32 "", flash_cris);
LOG_WARNING("Error setting flash page protection, flash_cris 0x%" PRIx32, flash_cris);
target_write_u32(target, FLASH_CRIS, 0);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -1035,7 +1035,7 @@ static int stellaris_write_block(struct flash_bank *bank,
if (wcount * 4 < buf_min)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32,
bank, buffer, offset, wcount);
/* flash write code */
@@ -1115,7 +1115,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32,
bank, buffer, offset, count);
if (stellaris_info->did1 == 0)
@@ -1153,7 +1153,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
/* if an error occurred, we examine the reason, and quit */
target_read_u32(target, FLASH_CRIS, &flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32, flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
} else {
@@ -1165,7 +1165,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
while (words_remaining > 0) {
if (!(address & 0xff))
LOG_DEBUG("0x%" PRIx32 "", address);
LOG_DEBUG("0x%" PRIx32, address);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
@@ -1189,7 +1189,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
memcpy(last_word, buffer+bytes_written, bytes_remaining);
if (!(address & 0xff))
LOG_DEBUG("0x%" PRIx32 "", address);
LOG_DEBUG("0x%" PRIx32, address);
/* Program one word */
target_write_u32(target, FLASH_FMA, address);
@@ -1205,7 +1205,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
/* Check access violations */
target_read_u32(target, FLASH_CRIS, &flash_cris);
if (flash_cris & (AMASK)) {
LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
LOG_DEBUG("flash_cris 0x%" PRIx32, flash_cris);
return ERROR_FLASH_OPERATION_FAILED;
}
return ERROR_OK;

10
src/flash/nor/stm32f1x.c
View File

@@ -170,7 +170,7 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
retval = stm32x_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_BSY) == 0)
break;
if (timeout-- <= 0) {
@@ -825,7 +825,7 @@ static int stm32x_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
LOG_INFO("device id = 0x%08" PRIx32, dbgmcu_idcode);
uint16_t device_id = dbgmcu_idcode & 0xfff;
uint16_t rev_id = dbgmcu_idcode >> 16;
@@ -1444,8 +1444,8 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
if (optionbyte & (1 << OPT_ERROR))
command_print(CMD, "option byte complement error");
command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
command_print(CMD, "option byte register = 0x%" PRIx32, optionbyte);
command_print(CMD, "write protection register = 0x%" PRIx32, protection);
command_print(CMD, "read protection: %s",
(optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
@@ -1465,7 +1465,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
if (stm32x_info->has_dual_banks)
command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
command_print(CMD, "user data = 0x%02" PRIx16, user_data);
return ERROR_OK;
}

4
src/flash/nor/stm32l4x.c
View File

@@ -981,7 +981,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & stm32l4_info->sr_bsy_mask) == 0)
break;
if (timeout-- <= 0) {
@@ -2419,7 +2419,7 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command)
if (retval != ERROR_OK)
return retval;
command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32, reg_addr, value);
return retval;
}

4
src/flash/nor/stm32lx.c
View File

@@ -745,7 +745,7 @@ static int stm32lx_probe(struct flash_bank *bank)
stm32lx_info->idcode = device_id;
LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
LOG_DEBUG("device id = 0x%08" PRIx32, device_id);
for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
if ((device_id & 0xfff) == stm32lx_parts[n].id) {
@@ -1204,7 +1204,7 @@ static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int tim
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("status: 0x%" PRIx32 "", status);
LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_SR__BSY) == 0)
break;

2
src/flash/nor/str7x.c
View File

@@ -335,7 +335,7 @@ static int str7x_erase(struct flash_bank *bank, unsigned int first,
for (unsigned int i = first; i <= last; i++)
sectors |= str7x_info->sector_bits[i];
LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
LOG_DEBUG("sectors: 0x%" PRIx32, sectors);
/* clear FLASH_ER register */
err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);

2
src/flash/nor/str9xpec.c
View File

@@ -735,7 +735,7 @@ COMMAND_HANDLER(str9xpec_handle_part_id_command)
idcode = buf_get_u32(buffer, 0, 32);
command_print(CMD, "str9xpec part id: 0x%8.8" PRIx32 "", idcode);
command_print(CMD, "str9xpec part id: 0x%8.8" PRIx32, idcode);
free(buffer);

56
src/flash/nor/tms470.c
View File

@@ -125,7 +125,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
/* read and parse the device identification register */
target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
LOG_INFO("device_ident_reg = 0x%08" PRIx32, device_ident_reg);
if ((device_ident_reg & 7) == 0) {
LOG_WARNING("Cannot identify target as a TMS470 family.");
@@ -300,7 +300,7 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command)
if (keys_set) {
command_print(CMD,
"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32,
flash_keys[0],
flash_keys[1],
flash_keys[2],
@@ -419,7 +419,7 @@ static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
*/
target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32, key_set[i]);
target_write_u32(target, 0xFFE89C0C, key_set[i]);
}
@@ -500,7 +500,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
fmmac2 &= ~0x0007;
fmmac2 |= (tms470_info->ordinal & 7);
target_write_u32(target, 0xFFE8BC04, fmmac2);
LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
LOG_DEBUG("set fmmac2 = 0x%04" PRIx32, fmmac2);
/*
* Disable level 1 sector protection by setting bit 15 of FMMAC1.
@@ -508,7 +508,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
target_read_u32(target, 0xFFE8BC00, &fmmac1);
fmmac1 |= 0x8000;
target_write_u32(target, 0xFFE8BC00, fmmac1);
LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
LOG_DEBUG("set fmmac1 = 0x%04" PRIx32, fmmac1);
/*
* FMTCREG = 0x2fc0;
@@ -542,7 +542,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
LOG_DEBUG("set fmptr3 = 0x9b64");
}
target_write_u32(target, 0xFFE8A080, fmmaxep);
LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
LOG_DEBUG("set fmmaxep = 0x%04" PRIx32, fmmaxep);
/*
* FMPTR4 = 0xa000
@@ -562,56 +562,56 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7));
delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
LOG_DEBUG("set fmpsetup = 0x%04" PRIx32, (delay << 4) | (delay << 8));
/*
* FMPVEVACCESS, based on delay.
*/
k = delay | (delay << 8);
target_write_u32(target, 0xFFE8A05C, k);
LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32, k);
/*
* FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
*/
k <<= 1;
target_write_u32(target, 0xFFE8A034, k);
LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpchold = 0x%04" PRIx32, k);
target_write_u32(target, 0xFFE8A040, k);
LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32, k);
target_write_u32(target, 0xFFE8A024, k);
LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32, k);
/*
* FMCVACCESS, based on delay.
*/
k = delay * 16;
target_write_u32(target, 0xFFE8A060, k);
LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32, k);
/*
* FMCSETUP, based on delay.
*/
k = 0x3000 | delay * 20;
target_write_u32(target, 0xFFE8A020, k);
LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmcsetup = 0x%04" PRIx32, k);
/*
* FMEHOLD, based on delay.
*/
k = (delay * 20) << 2;
target_write_u32(target, 0xFFE8A038, k);
LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
LOG_DEBUG("set fmehold = 0x%04" PRIx32, k);
/*
* PWIDTH, CWIDTH, EWIDTH, based on delay.
*/
target_write_u32(target, 0xFFE8A050, delay * 8);
LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
LOG_DEBUG("set fmpwidth = 0x%04" PRIx32, delay * 8);
target_write_u32(target, 0xFFE8A058, delay * 1000);
LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
LOG_DEBUG("set fmcwidth = 0x%04" PRIx32, delay * 1000);
target_write_u32(target, 0xFFE8A054, delay * 5400);
LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
LOG_DEBUG("set fmewidth = 0x%04" PRIx32, delay * 5400);
return result;
}
@@ -625,7 +625,7 @@ static int tms470_flash_status(struct flash_bank *bank)
uint32_t fmmstat;
target_read_u32(target, 0xFFE8BC0C, &fmmstat);
LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
LOG_DEBUG("set fmmstat = 0x%04" PRIx32, fmmstat);
if (fmmstat & 0x0080) {
LOG_WARNING("tms470 flash command: erase still active after busy clear.");
@@ -680,7 +680,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
*/
target_read_u32(target, 0xFFFFFFDC, &glbctrl);
target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32, glbctrl | 0x10);
/* Force normal read mode. */
target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
@@ -697,11 +697,11 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
if (sector < 16) {
target_read_u32(target, 0xFFE88008, &fmbsea);
target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
LOG_DEBUG("set fmbsea = 0x%04" PRIx32, fmbsea | (1 << sector));
} else {
target_read_u32(target, 0xFFE8800C, &fmbseb);
target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
LOG_DEBUG("set fmbseb = 0x%04" PRIx32, fmbseb | (1 << (sector - 16)));
}
bank->sectors[sector].is_protected = 0;
@@ -729,17 +729,17 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
if (sector < 16) {
target_write_u32(target, 0xFFE88008, fmbsea);
LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
LOG_DEBUG("set fmbsea = 0x%04" PRIx32, fmbsea);
bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
} else {
target_write_u32(target, 0xFFE8800C, fmbseb);
LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
LOG_DEBUG("set fmbseb = 0x%04" PRIx32, fmbseb);
bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
}
target_write_u32(target, 0xFFE89C00, orig_fmregopt);
LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
LOG_DEBUG("set fmregopt = 0x%08" PRIx32, orig_fmregopt);
target_write_u32(target, 0xFFFFFFDC, glbctrl);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
LOG_DEBUG("set glbctrl = 0x%08" PRIx32, glbctrl);
return result;
}
@@ -920,7 +920,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
if (word != 0xffff) {
LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
LOG_INFO("writing 0x%04x at 0x%08" PRIx32, word, addr);
/* clear status register */
target_write_u16(target, addr, 0x0040);
@@ -940,7 +940,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
} while (fmmstat & 0x0100);
if (fmmstat & 0x3ff) {
LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
LOG_ERROR("fmstat = 0x%04" PRIx32, fmmstat);
LOG_ERROR(
"Could not program word 0x%04x at address 0x%08" PRIx32 ".",
word,
@@ -949,7 +949,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
break;
}
} else
LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
LOG_INFO("skipping 0xffff at 0x%08" PRIx32, addr);
}
/* restore */

10
src/flash/nor/w600.c
View File

@@ -128,13 +128,13 @@ static int w600_start_do(struct flash_bank *bank, uint32_t cmd, uint32_t addr,
if (len > 0)
cmd |= QFLASH_CMD_DATALEN(len - 1) | QFLASH_CMD_DATA;
LOG_DEBUG("WRITE CMD: 0x%08" PRIx32 "", cmd);
LOG_DEBUG("WRITE CMD: 0x%08" PRIx32, cmd);
int retval = target_write_u32(target, QFLASH_CMD_INFO, cmd);
if (retval != ERROR_OK)
return retval;
addr |= QFLASH_START;
LOG_DEBUG("WRITE START: 0x%08" PRIx32 "", addr);
LOG_DEBUG("WRITE START: 0x%08" PRIx32, addr);
retval = target_write_u32(target, QFLASH_CMD_START, addr);
if (retval != ERROR_OK)
return retval;
@@ -148,7 +148,7 @@ static int w600_start_do(struct flash_bank *bank, uint32_t cmd, uint32_t addr,
LOG_DEBUG("READ START...");
retval = target_read_u32(target, QFLASH_CMD_START, &status);
if (retval == ERROR_OK)
LOG_DEBUG("READ START: 0x%08" PRIx32 "", status);
LOG_DEBUG("READ START: 0x%08" PRIx32, status);
else
LOG_DEBUG("READ START FAILED");
@@ -283,7 +283,7 @@ static int w600_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
LOG_INFO("flash_id id = 0x%08" PRIx32 "", flash_id);
LOG_INFO("flash_id id = 0x%08" PRIx32, flash_id);
w600_info->id = flash_id;
w600_info->param = NULL;
for (i = 0; i < ARRAY_SIZE(w600_param); i++) {
@@ -360,7 +360,7 @@ static int get_w600_info(struct flash_bank *bank, struct command_invocation *cmd
if (retval != ERROR_OK)
return retval;
command_print_sameline(cmd, "w600 : 0x%08" PRIx32 "", flash_id);
command_print_sameline(cmd, "w600 : 0x%08" PRIx32, flash_id);
return ERROR_OK;
}