auracaster/openocd
3
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

openocd: drop empty string suffix from format strings

Browse Source 
Format strings are often split to allow using the conversion
specifiers macros from <inttypes.h>.
When the format string ends with one of such macros, there is no
need to add an empty string "" after the macro.

In current code we have 203 cases of empty string present, against
1159 cases of string ending with the macro.

Uniform the style across OpenOCD by removing the empty string.

Don't modify the files 'angie.c' and 'max32xxx.c' as they are
already changed by other independent commits.

Change-Id: I23f1120101ce1da67c6578635fc6507a58c803e9
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9065
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2025-08-01 17:06:05 +02:00
parent 9fe3780432
commit 003cb92cd5
52 changed files with 200 additions and 200 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/target/arm11.c
View File

@@ -469,7 +469,7 @@ static int arm11_resume(struct target *target, bool current,
for (bp = target->breakpoints; bp; bp = bp->next) {
if (bp->address == address) {
LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
LOG_DEBUG("must step over %08" TARGET_PRIxADDR, bp->address);
arm11_step(target, true, 0, false);
break;
}
@@ -802,7 +802,7 @@ static int arm11_read_memory_inner(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32,
address,
size,
count);
@@ -900,7 +900,7 @@ static int arm11_write_memory_inner(struct target *target,
return ERROR_TARGET_NOT_HALTED;
}
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32 "",
LOG_DEBUG("ADDR %08" PRIx32 " SIZE %08" PRIx32 " COUNT %08" PRIx32,
address,
size,
count);
@@ -1264,7 +1264,7 @@ COMMAND_HANDLER(arm11_handle_vcr)
return ERROR_COMMAND_SYNTAX_ERROR;
}
LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
LOG_INFO("VCR 0x%08" PRIx32, arm11->vcr);
return ERROR_OK;
}

2
src/target/arm720t.c
View File

@@ -197,7 +197,7 @@ static int arm720t_post_debug_entry(struct target *target)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm720t->cp15_control_reg);
arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =

18
src/target/arm7_9_common.c
View File

@@ -643,7 +643,7 @@ int arm7_9_execute_sys_speed(struct target *target)
keep_alive();
}
if (timeout) {
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "",
LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32,
buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
return ERROR_TARGET_TIMEOUT;
}
@@ -1332,7 +1332,7 @@ static int arm7_9_debug_entry(struct target *target)
for (i = 0; i <= 15; i++) {
struct reg *r = arm_reg_current(arm, i);
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
LOG_DEBUG("r%i: 0x%8.8" PRIx32, i, context[i]);
buf_set_u32(r->value, 0, 32, context[i]);
/* r0 and r15 (pc) have to be restored later */
@@ -1340,7 +1340,7 @@ static int arm7_9_debug_entry(struct target *target)
r->valid = true;
}
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
LOG_DEBUG("entered debug state at PC 0x%" PRIx32, context[15]);
/* exceptions other than USR & SYS have a saved program status register */
if (arm->spsr) {
@@ -1594,7 +1594,7 @@ static int arm7_9_restore_context(struct target *target)
struct arm_reg *reg_arch_info;
reg_arch_info = reg->arch_info;
if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) {
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "",
LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32,
i,
buf_get_u32(reg->value, 0, 32));
arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
@@ -1744,7 +1744,7 @@ int arm7_9_resume(struct target *target,
uint32_t current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
return retval;
}
@@ -1789,7 +1789,7 @@ int arm7_9_resume(struct target *target,
LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
buf_get_u32(arm->pc->value, 0, 32));
LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR, breakpoint->address);
retval = arm7_9_set_breakpoint(target, breakpoint);
if (retval != ERROR_OK)
return retval;
@@ -1937,7 +1937,7 @@ int arm7_9_step(struct target *target, bool current, target_addr_t address,
uint32_t current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
return retval;
}
@@ -2116,7 +2116,7 @@ int arm7_9_read_memory(struct target *target,
int retval;
int last_reg = 0;
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
if (target->state != TARGET_HALTED) {
@@ -2636,7 +2636,7 @@ int arm7_9_bulk_write_memory(struct target *target,
uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
if (endaddress != (address + count*4)) {
LOG_ERROR(
"DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "",
"DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32,
(address + count*4),
endaddress);
retval = ERROR_FAIL;

4
src/target/arm926ejs.c
View File

@@ -427,7 +427,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm926ejs->cp15_control_reg);
if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) {
uint32_t cache_type_reg;
@@ -458,7 +458,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32,
arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
uint32_t cache_dbg_ctrl;

12
src/target/arm_disassembler.c
View File

@@ -324,7 +324,7 @@ static int evaluate_blx_imm(uint32_t opcode,
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "",
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32,
address,
opcode,
target_address);
@@ -596,7 +596,7 @@ static int evaluate_load_store(uint32_t opcode,
if (!i) { /* #+-<offset_12> */
uint32_t offset_12 = (opcode & 0xfff);
if (offset_12)
snprintf(offset, 32, ", #%s0x%" PRIx32 "", (u) ? "" : "-", offset_12);
snprintf(offset, 32, ", #%s0x%" PRIx32, (u) ? "" : "-", offset_12);
else
snprintf(offset, 32, "%s", "");
@@ -1079,7 +1079,7 @@ static int evaluate_misc_load_store(uint32_t opcode,
if (i) {/* Immediate offset/index (#+-<offset_8>)*/
uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
snprintf(offset, 32, "#%s0x%" PRIx32 "", (u) ? "" : "-", offset_8);
snprintf(offset, 32, "#%s0x%" PRIx32, (u) ? "" : "-", offset_8);
instruction->info.load_store.offset_mode = 0;
instruction->info.load_store.offset.offset = offset_8;
@@ -1546,7 +1546,7 @@ static int evaluate_misc_instr(uint32_t opcode,
snprintf(instruction->text,
128,
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32,
address,
opcode,
mnemonic,
@@ -1790,7 +1790,7 @@ static int evaluate_data_proc(uint32_t opcode,
immediate = ror(immed_8, rotate_imm * 2);
snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);
snprintf(shifter_operand, 32, "#0x%" PRIx32, immediate);
instruction->info.data_proc.variant = 0;
instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
@@ -2628,7 +2628,7 @@ static int evaluate_breakpoint_thumb(uint16_t opcode,
instruction->type = ARM_BKPT;
snprintf(instruction->text, 128,
"0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t%#2.2" PRIx32 "",
"0x%8.8" PRIx32 " 0x%4.4x \tBKPT\t%#2.2" PRIx32,
address, opcode, imm);
return ERROR_OK;

2
src/target/armv4_5.c
View File

@@ -1564,7 +1564,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).value, 0, 32);
if (regvalue != context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).name, context[i]);
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,

4
src/target/armv4_5_mmu.c
View File

@@ -31,7 +31,7 @@ int armv4_5_mmu_translate_va(struct target *target,
return retval;
first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
LOG_DEBUG("1st lvl desc: %8.8" PRIx32, first_lvl_descriptor);
if ((first_lvl_descriptor & 0x3) == 0) {
LOG_ERROR("Address translation failure");
@@ -68,7 +68,7 @@ int armv4_5_mmu_translate_va(struct target *target,
second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
LOG_DEBUG("2nd lvl desc: %8.8" PRIx32, second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 0) {
LOG_ERROR("Address translation failure");

14
src/target/avr32_ap7k.c
View File

@@ -117,7 +117,7 @@ static int avr32_write_core_reg(struct target *target, int num)
reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32);
ap7k->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, reg_value);
ap7k->core_cache->reg_list[num].valid = true;
ap7k->core_cache->reg_list[num].dirty = false;
@@ -337,7 +337,7 @@ static int avr32_ap7k_resume(struct target *target, bool current,
/* Single step past breakpoint at current address */
breakpoint = breakpoint_find(target, resume_pc);
if (breakpoint) {
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR, breakpoint->address);
#if 0
avr32_ap7k_unset_breakpoint(target, breakpoint);
avr32_ap7k_single_step_core(target);
@@ -372,11 +372,11 @@ static int avr32_ap7k_resume(struct target *target, bool current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
return ERROR_OK;
@@ -425,7 +425,7 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address,
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address,
size,
count);
@@ -465,7 +465,7 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address,
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address,
size,
count);
@@ -548,7 +548,7 @@ static int avr32_ap7k_arch_state(struct target *target)
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32,
debug_reason_name(target), ap7k->jtag.dpc);
return ERROR_OK;

8
src/target/cortex_m.c
View File

@@ -554,7 +554,7 @@ static int cortex_m_clear_halt(struct target *target)
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32, cortex_m->nvic_dfsr);
return ERROR_OK;
}
@@ -616,7 +616,7 @@ static int cortex_m_endreset_event(struct target *target)
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32, dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
@@ -1911,7 +1911,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
comparator_list[fp_num].fpcr_value = fpcr_value;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32,
fp_num,
comparator_list[fp_num].fpcr_value);
if (!cortex_m->fpb_enabled) {
@@ -2773,7 +2773,7 @@ int cortex_m_examine(struct target *target)
else
LOG_TARGET_INFO(target, "The erratum 3092511 workaround will resume after an incorrect halt");
}
LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32, cpuid);
if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
uint32_t mvfr0;

4
src/target/dsp563xx.c
View File

@@ -1517,7 +1517,7 @@ static int dsp563xx_read_memory_core(struct target *target,
uint8_t *b;
LOG_DEBUG(
"memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
"memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
mem_type,
address,
size,
@@ -1698,7 +1698,7 @@ static int dsp563xx_write_memory_core(struct target *target,
const uint8_t *b;
LOG_DEBUG(
"memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
"memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
mem_type,
address,
size,

2
src/target/embeddedice.c
View File

@@ -502,7 +502,7 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
{
struct embeddedice_reg *ice_reg = reg->arch_info;
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
LOG_DEBUG("%i: 0x%8.8" PRIx32, ice_reg->addr, value);
arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);

2
src/target/etb.c
View File

@@ -287,7 +287,7 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
uint8_t reg_addr = etb_reg->addr & 0x7f;
struct scan_field fields[3];
LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
LOG_DEBUG("%i: 0x%8.8" PRIx32, (int)(etb_reg->addr), value);
etb_scann(etb_reg->etb, 0x0);
etb_set_instr(etb_reg->etb, 0xc);

10
src/target/etm.c
View File

@@ -584,7 +584,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
return ERROR_COMMAND_SYNTAX_ERROR;
}
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
LOG_DEBUG("%s (%u): 0x%8.8" PRIx32, r->name, reg_addr, value);
retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
if (retval != ERROR_OK)
@@ -986,7 +986,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
command_print(cmd, "data abort");
else {
command_print(cmd,
"exception vector 0x%2.2" PRIx32 "",
"exception vector 0x%2.2" PRIx32,
ctx->last_branch);
ctx->current_pc = ctx->last_branch;
ctx->pipe_index++;
@@ -1044,7 +1044,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
if (ctx->ptr_ok)
command_print(cmd,
"address: 0x%8.8" PRIx32 "",
"address: 0x%8.8" PRIx32,
ctx->last_ptr);
}
@@ -1059,7 +1059,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
if (etmv1_data(ctx, 4, &data) != 0)
return ERROR_ETM_ANALYSIS_FAILED;
command_print(cmd,
"data: 0x%8.8" PRIx32 "",
"data: 0x%8.8" PRIx32,
data);
}
}
@@ -1069,7 +1069,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
if (etmv1_data(ctx, arm_access_size(&instruction),
&data) != 0)
return ERROR_ETM_ANALYSIS_FAILED;
command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
command_print(cmd, "data: 0x%8.8" PRIx32, data);
}
}

2
src/target/feroceon.c
View File

@@ -555,7 +555,7 @@ static int feroceon_bulk_write_memory(struct target *target,
if (endaddress != address + count*4) {
LOG_ERROR("DCC write failed,"
" expected end address 0x%08" TARGET_PRIxADDR
" got 0x%0" PRIx32 "",
" got 0x%0" PRIx32,
address + count*4, endaddress);
retval = ERROR_FAIL;
}

6
src/target/image.c
View File

@@ -670,7 +670,7 @@ static int image_elf32_read_section(struct image *image,
if (offset < field32(elf, segment->p_filesz)) {
/* maximal size present in file for the current segment */
read_size = MIN(size, field32(elf, segment->p_filesz) - offset);
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR, read_size,
field32(elf, segment->p_offset) + offset);
/* read initialized area of the segment */
retval = fileio_seek(elf->fileio, field32(elf, segment->p_offset) + offset);
@@ -713,7 +713,7 @@ static int image_elf64_read_section(struct image *image,
if (offset < field64(elf, segment->p_filesz)) {
/* maximal size present in file for the current segment */
read_size = MIN(size, field64(elf, segment->p_filesz) - offset);
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR, read_size,
field64(elf, segment->p_offset) + offset);
/* read initialized area of the segment */
retval = fileio_seek(elf->fileio, field64(elf, segment->p_offset) + offset);
@@ -1088,7 +1088,7 @@ int image_read_section(struct image *image,
/* don't read past the end of a section */
if (offset + size > image->sections[section].size) {
LOG_DEBUG(
"read past end of section: 0x%8.8" TARGET_PRIxADDR " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32 "",
"read past end of section: 0x%8.8" TARGET_PRIxADDR " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32,
offset,
size,
image->sections[section].size);

6
src/target/mips32.c
View File

@@ -374,7 +374,7 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
LOG_DEBUG("read core reg %i value 0x%" PRIx64, num, reg_value);
return ERROR_OK;
}
@@ -419,7 +419,7 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
mips32->core_regs.gpr[cnum] = (uint32_t)reg_value;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
@@ -485,7 +485,7 @@ int mips32_arch_state(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32,
mips_isa_strings[mips32->isa_mode],
debug_reason_name(target),
buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));

4
src/target/mips64.c
View File

@@ -283,7 +283,7 @@ static int mips64_write_core_reg(struct target *target, int num)
reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
mips64->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
mips64->core_cache->reg_list[num].valid = true;
mips64->core_cache->reg_list[num].dirty = false;
@@ -361,7 +361,7 @@ int mips64_arch_state(struct target *target)
exit(-1);
}
LOG_USER("target halted due to %s, pc: 0x%" PRIx64 "",
LOG_USER("target halted due to %s, pc: 0x%" PRIx64,
debug_reason_name(target), buf_get_u64(pc->value, 0, 64));
return ERROR_OK;

2
src/target/mips_ejtag.c
View File

@@ -245,7 +245,7 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
/* break bit will be cleared by hardware */
ejtag_ctrl = ejtag_info->ejtag_ctrl;
mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32 "", ejtag_ctrl);
LOG_DEBUG("ejtag_ctrl: 0x%8.8" PRIx32, ejtag_ctrl);
if ((ejtag_ctrl & EJTAG_CTRL_BRKST) == 0)
goto error;

16
src/target/mips_m4k.c
View File

@@ -486,11 +486,11 @@ static int mips_m4k_internal_restore(struct target *target, bool current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
return ERROR_OK;
@@ -638,7 +638,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
ejtag_info->ejtag_ibm_offs, 0x00000000);
target_write_u32(target, comparator_list[bp_num].reg_address +
ejtag_info->ejtag_ibc_offs, 1);
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32,
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
} else if (breakpoint->type == BKPT_SOFT) {
@@ -928,7 +928,7 @@ static int mips_m4k_set_watchpoint(struct target *target,
/* TODO: probably this value is ignored on 2.0 */
target_write_u32(target, comparator_list[wp_num].reg_address +
ejtag_info->ejtag_dbv_offs, 0);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32, wp_num, comparator_list[wp_num].bp_value);
return ERROR_OK;
}
@@ -1012,7 +1012,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address,
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
if (target->state != TARGET_HALTED) {
@@ -1077,7 +1077,7 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address,
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
if (target->state != TARGET_HALTED) {
@@ -1204,7 +1204,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
int retval;
int write_t = 1;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32,
address, count);
/* check alignment */
@@ -1270,7 +1270,7 @@ static int mips_m4k_bulk_read_memory(struct target *target, target_addr_t addres
int retval;
int write_t = 0;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32,
address, count);
/* check alignment */

14
src/target/mips_mips64.c
View File

@@ -473,7 +473,7 @@ static int mips_mips64_set_watchpoint(struct target *target,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx64 "", wp_num, c->bp_value);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx64, wp_num, c->bp_value);
return ERROR_OK;
}
@@ -642,7 +642,7 @@ static int mips_mips64_resume(struct target *target, bool current,
/* Single step past breakpoint at current address */
bp = breakpoint_find(target, (uint64_t) resume_pc);
if (bp) {
LOG_DEBUG("unset breakpoint at 0x%16.16" PRIx64 "",
LOG_DEBUG("unset breakpoint at 0x%16.16" PRIx64,
bp->address);
retval = mips_mips64_unset_breakpoint(target, bp);
if (retval != ERROR_OK)
@@ -682,7 +682,7 @@ static int mips_mips64_resume(struct target *target, bool current,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("target resumed at 0x%" PRIx64 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx64, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
retval = target_call_event_callbacks(target,
@@ -690,7 +690,7 @@ static int mips_mips64_resume(struct target *target, bool current,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("target debug resumed at 0x%" PRIx64 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx64, resume_pc);
}
return ERROR_OK;
@@ -911,7 +911,7 @@ static int mips_mips64_read_memory(struct target *target, uint64_t address,
} else
t = buffer;
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
retval = mips64_pracc_read_mem(ejtag_info, address, size, count,
(void *)t);
@@ -949,7 +949,7 @@ static int mips_mips64_bulk_write_memory(struct target *target,
struct working_area *fast_data_area;
int retval;
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", count: 0x%8.8" PRIx32,
address, count);
if (address & 0x7)
@@ -1066,7 +1066,7 @@ static int mips_mips64_write_memory(struct target *target, uint64_t address,
buffer = t;
}
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
address, size, count);
retval = mips64_pracc_write_mem(ejtag_info, address, size, count,

14
src/target/stm8.c
View File

@@ -1094,11 +1094,11 @@ static int stm8_resume(struct target *target, bool current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
return ERROR_OK;
@@ -1173,7 +1173,7 @@ static int stm8_read_core_reg(struct target *target, unsigned int num)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = stm8->core_regs[num];
LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num, reg_value);
LOG_DEBUG("read core reg %i value 0x%" PRIx32, num, reg_value);
buf_set_u32(stm8->core_cache->reg_list[num].value, 0, 32, reg_value);
stm8->core_cache->reg_list[num].valid = true;
stm8->core_cache->reg_list[num].dirty = false;
@@ -1193,7 +1193,7 @@ static int stm8_write_core_reg(struct target *target, unsigned int num)
reg_value = buf_get_u32(stm8->core_cache->reg_list[num].value, 0, 32);
stm8->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, reg_value);
stm8->core_cache->reg_list[num].valid = true;
stm8->core_cache->reg_list[num].dirty = false;
@@ -1327,7 +1327,7 @@ static int stm8_arch_state(struct target *target)
{
struct stm8_common *stm8 = target_to_stm8(target);
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32,
debug_reason_name(target),
buf_get_u32(stm8->core_cache->reg_list[STM8_PC].value, 0, 32));
@@ -1438,7 +1438,7 @@ static int stm8_set_breakpoint(struct target *target,
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx32,
breakpoint->unique_id,
bp_num, comparator_list[bp_num].bp_value);
} else if (breakpoint->type == BKPT_SOFT) {
@@ -1626,7 +1626,7 @@ static int stm8_set_watchpoint(struct target *target,
watchpoint_set(watchpoint, wp_num);
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "",
LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32,
wp_num,
comparator_list[wp_num].bp_value);

16
src/target/target.c
View File

@@ -2544,7 +2544,7 @@ int target_read_u64(struct target *target, target_addr_t address, uint64_t *valu
if (retval == ERROR_OK) {
*value = target_buffer_get_u64(target, value_buf);
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64,
address,
*value);
} else {
@@ -2568,7 +2568,7 @@ int target_read_u32(struct target *target, target_addr_t address, uint32_t *valu
if (retval == ERROR_OK) {
*value = target_buffer_get_u32(target, value_buf);
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32,
address,
*value);
} else {
@@ -2635,7 +2635,7 @@ int target_write_u64(struct target *target, target_addr_t address, uint64_t valu
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64,
address,
value);
@@ -2656,7 +2656,7 @@ int target_write_u32(struct target *target, target_addr_t address, uint32_t valu
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32,
address,
value);
@@ -2716,7 +2716,7 @@ int target_write_phys_u64(struct target *target, target_addr_t address, uint64_t
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%16.16" PRIx64,
address,
value);
@@ -2737,7 +2737,7 @@ int target_write_phys_u32(struct target *target, target_addr_t address, uint32_t
return ERROR_FAIL;
}
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32 "",
LOG_DEBUG("address: " TARGET_ADDR_FMT ", value: 0x%8.8" PRIx32,
address,
value);
@@ -3973,7 +3973,7 @@ static int handle_bp_command_set(struct command_invocation *cmd,
retval = context_breakpoint_add(target, asid, length, hw);
/* error is always logged in context_breakpoint_add(), do not print it again */
if (retval == ERROR_OK)
command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32 "", asid);
command_print(cmd, "Context breakpoint set at 0x%8.8" PRIx32, asid);
} else {
if (!target->type->add_hybrid_breakpoint) {
@@ -3983,7 +3983,7 @@ static int handle_bp_command_set(struct command_invocation *cmd,
retval = hybrid_breakpoint_add(target, addr, asid, length, hw);
/* error is always logged in hybrid_breakpoint_add(), do not print it again */
if (retval == ERROR_OK)
command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32 "", asid);
command_print(cmd, "Hybrid breakpoint set at 0x%8.8" PRIx32, asid);
}
return retval;
}

2
src/target/trace.c
View File

@@ -115,7 +115,7 @@ COMMAND_HANDLER(handle_trace_history_command)
if (trace->trace_history[i % trace->trace_history_size] < trace->num_trace_points) {
uint32_t address;
address = trace->trace_points[trace->trace_history[i % trace->trace_history_size]].address;
command_print(CMD, "trace point %i: 0x%8.8" PRIx32 "",
command_print(CMD, "trace point %i: 0x%8.8" PRIx32,
(int)(trace->trace_history[i % trace->trace_history_size]),
address);
} else

6
src/target/x86_32_common.c
View File

@@ -1027,7 +1027,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
if (read_phys_mem(t, physaddr, 1, 1, bp->orig_instr))
return ERROR_FAIL;
LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8 "", *bp->orig_instr);
LOG_DEBUG("set software breakpoint - orig byte=0x%02" PRIx8, *bp->orig_instr);
/* just write the instruction trap byte */
if (write_phys_mem(t, physaddr, 1, 1, &opcode))
@@ -1040,7 +1040,7 @@ static int set_swbp(struct target *t, struct breakpoint *bp)
if (readback != SW_BP_OPCODE) {
LOG_ERROR("%s software breakpoint error at " TARGET_ADDR_FMT ", check memory",
__func__, bp->address);
LOG_ERROR("%s readback=0x%02" PRIx8 " orig=0x%02" PRIx8 "",
LOG_ERROR("%s readback=0x%02" PRIx8 " orig=0x%02" PRIx8,
__func__, readback, *bp->orig_instr);
return ERROR_FAIL;
}
@@ -1089,7 +1089,7 @@ static int unset_swbp(struct target *t, struct breakpoint *bp)
} else {
LOG_ERROR("%s software breakpoint remove error at " TARGET_ADDR_FMT ", check memory",
__func__, bp->address);
LOG_ERROR("%s current=0x%02" PRIx8 " orig=0x%02" PRIx8 "",
LOG_ERROR("%s current=0x%02" PRIx8 " orig=0x%02" PRIx8,
__func__, current_instr, *bp->orig_instr);
return ERROR_FAIL;
}

22
src/target/xscale.c
View File

@@ -640,7 +640,7 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
int word;
struct scan_field fields[2];
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32, va);
/* LDIC into IR */
xscale_jtag_set_instr(target->tap,
@@ -856,24 +856,24 @@ static int xscale_debug_entry(struct target *target)
buf_set_u32(arm->core_cache->reg_list[0].value, 0, 32, buffer[0]);
arm->core_cache->reg_list[0].dirty = true;
arm->core_cache->reg_list[0].valid = true;
LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
LOG_DEBUG("r0: 0x%8.8" PRIx32, buffer[0]);
/* move pc from buffer to register cache */
buf_set_u32(arm->pc->value, 0, 32, buffer[1]);
arm->pc->dirty = true;
arm->pc->valid = true;
LOG_DEBUG("pc: 0x%8.8" PRIx32 "", buffer[1]);
LOG_DEBUG("pc: 0x%8.8" PRIx32, buffer[1]);
/* move data from buffer to register cache */
for (i = 1; i <= 7; i++) {
buf_set_u32(arm->core_cache->reg_list[i].value, 0, 32, buffer[1 + i]);
arm->core_cache->reg_list[i].dirty = true;
arm->core_cache->reg_list[i].valid = true;
LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, buffer[i + 1]);
LOG_DEBUG("r%i: 0x%8.8" PRIx32, i, buffer[i + 1]);
}
arm_set_cpsr(arm, buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32 "", buffer[9]);
LOG_DEBUG("cpsr: 0x%8.8" PRIx32, buffer[9]);
if (!is_arm_mode(arm->core_mode)) {
target->state = TARGET_UNKNOWN;
@@ -1159,7 +1159,7 @@ static int xscale_resume(struct target *target, bool current,
uint32_t current_opcode;
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
}
@@ -1184,7 +1184,7 @@ static int xscale_resume(struct target *target, bool current,
/* send register */
xscale_send_u32(target,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32,
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
@@ -1248,7 +1248,7 @@ static int xscale_resume(struct target *target, bool current,
for (i = 7; i >= 0; i--) {
/* send register */
xscale_send_u32(target, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "",
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32,
i, buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
@@ -1293,7 +1293,7 @@ static int xscale_step_inner(struct target *target, bool current,
target_read_u32(target, current_pc, &current_opcode);
LOG_ERROR(
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
"BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
current_opcode);
return retval;
}
@@ -1337,7 +1337,7 @@ static int xscale_step_inner(struct target *target, bool current,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
if (retval != ERROR_OK)
return retval;
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32 "", i,
LOG_DEBUG("writing r%i with value 0x%8.8" PRIx32, i,
buf_get_u32(arm->core_cache->reg_list[i].value, 0, 32));
}
@@ -3557,7 +3557,7 @@ COMMAND_HANDLER(xscale_handle_cp15)
/* read cp15 control register */
xscale_get_reg(reg);
value = buf_get_u32(reg->value, 0, 32);
command_print(CMD, "%s (/%i): 0x%" PRIx32 "", reg->name, (int)(reg->size),
command_print(CMD, "%s (/%i): 0x%" PRIx32, reg->name, (int)(reg->size),
value);
} else if (CMD_ARGC == 2) {
uint32_t value;