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armv7a ,cortex a : add L1, L2 cache support, va to pa support

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This commit is contained in:
Michel Jaouen
2011-09-29 17:17:27 +02:00
committed by Øyvind Harboe
parent ef885d3b2a
commit 00ded4eb01
6 changed files with 911 additions and 230 deletions
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src/target/arm_dpm.c
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@@ -109,7 +109,7 @@ static int dpm_mcr(struct target *target, int cpnum,
/* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
* Routines *must* restore the original mode before returning!!
*/
static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
{
int retval;
uint32_t cpsr;