armv7a ,cortex a : add L1, L2 cache support, va to pa support

src/target/cortex_a.h

@@ -63,6 +63,10 @@ struct cortex_a8_common
 
 	/* Saved cp15 registers */
 	uint32_t cp15_control_reg;
+	/* latest cp15 register value written and cpsr processor mode */
+	uint32_t cp15_control_reg_curr;
+    enum arm_mode curr_mode;
+
 
 	/* Breakpoint register pairs */
 	int brp_num_context;
@@ -73,10 +77,8 @@ struct cortex_a8_common
 	/* Use cortex_a8_read_regs_through_mem for fast register reads */
 	int fast_reg_read;
 
-	/* Flag that helps to resolve what ttb to use: user or kernel */
-	int current_address_mode;
-
 	struct armv7a_common armv7a_common;
+
 };
 
 static inline struct cortex_a8_common *