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target/mips32: add dsp access support for gdb

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Change order of dsp register name array and removed hi0 and lo0
to comply with gdb definition of dsp in mips-dsp.xml, the regs
name array is now mapping corresponding dsp accumulator names
onto `mips32_regs` and `core_regs` instead of mapping to instr
arrays in dsp functions.
feature now requires a place to store cached dsp registers.
Add dsp registers to reg_list for gdb to access them.
Add dsp module enable detection to avoid DSP Disabled exception
while reading dsp accumulators.
Add dsp register reading procedure in `mips32_pracc_read_regs`
and writing procedure in `mips32_pracc_write_regs`.

Change-Id: Iacc335da030ab85989922c81aac7925b3dc17459
Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8476
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
This commit is contained in:
Walter Ji
2024-02-22 17:06:53 +08:00
committed by Antonio Borneo
parent ab31562131
commit 00ee9b09d9
3 changed files with 163 additions and 33 deletions
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src/target/mips32.h
+10 -1
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@@ -69,7 +69,7 @@
#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
#define MIPS32NUMDSPREGS 9
#define MIPS32NUMDSPREGS 7
/* Bit Mask indicating CP0 register supported by this core */
#define MIPS_CP0_MK4 0x0001
@@ -78,6 +78,7 @@
#define MIPS_CP0_IAPTIV 0x0008
/* CP0 Status register fields */
#define MIPS32_CP0_STATUS_MX_SHIFT 24
#define MIPS32_CP0_STATUS_FR_SHIFT 26
#define MIPS32_CP0_STATUS_CU1_SHIFT 29
@@ -211,6 +212,7 @@ static const struct mips32_cp0 {
enum {
MIPS32_PC = 37,
MIPS32_FIR = 71,
MIPS32_DSPCTL = 78,
MIPS32NUMCOREREGS
};
@@ -220,11 +222,13 @@ enum {
#define MIPS32_REG_FP_COUNT 32
#define MIPS32_REG_FPC_COUNT 2
#define MIPS32_REG_C0_COUNT 5
#define MIPS32_REG_DSP_COUNT 7
#define MIPS32_REGLIST_GP_INDEX 0
#define MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)
#define MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)
#define MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)
#define MIPS32_REGLIST_DSP_INDEX (MIPS32_REGLIST_C0_INDEX + MIPS32_REG_C0_COUNT)
#define MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0)
#define MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1)
@@ -238,6 +242,10 @@ enum {
#define MIPS32_REG_C0_PC_INDEX 3
#define MIPS32_REG_C0_GUESTCTL1_INDEX 4
#define MIPS32_REGLIST_DSP_DSPCTL_INDEX (MIPS32_REGLIST_DSP_INDEX + 6)
#define MIPS32_REG_DSP_DSPCTL_INDEX 6
enum mips32_isa_mode {
MIPS32_ISA_MIPS32 = 0,
MIPS32_ISA_MIPS16E = 1,
@@ -377,6 +385,7 @@ struct mips32_core_regs {
uint64_t fpr[MIPS32_REG_FP_COUNT];
uint32_t fpcr[MIPS32_REG_FPC_COUNT];
uint32_t cp0[MIPS32_REG_C0_COUNT];
uint32_t dsp[MIPS32_REG_DSP_COUNT];
};
struct mips32_common {