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tcl: add Espressif RISC-V config files

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Add configuration files for Espressif RISC-V based chips:
- ESP32-C2, ESP32-C3, ESP32-C6, ESP32-H2 target configs
- Board configs for builtin USB-JTAG and FTDI interfaces

while adding the new config files:
- Fix indentation in existing Espressif config files
- Adapt esp_common.cfg with RISC-V support
- Add explicit 'transport select jtag' to interface configs to avoid
  'DEPRECATED: auto-selecting transport' warning

Change-Id: I45fcbca2fe50888750e2e98a0a6773de86aad6d0
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9195
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
2025-11-01 14:36:27 +01:00
committed by Antonio Borneo
parent 52ea420dd2
commit 04c6a6ee0e
17 changed files with 659 additions and 44 deletions
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8
doc/openocd.texi
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@@ -630,7 +630,7 @@ emulation model of target hardware.
This is deprecated from Linux v5.3; prefer using @b{linuxgpiod}.
@item @b{esp_usb_jtag}
@* A JTAG driver to communicate with builtin debug modules of Espressif ESP32-C3 and ESP32-S3 chips using OpenOCD.
@* A JTAG driver to communicate with builtin debug modules of Espressif ESP32-C3, ESP32-C6, ESP32-H2 and ESP32-S3 chips using OpenOCD.
@item @b{ch347}
@* A JTAG driver that works with the WCH CH347F and CH347T chips.
@@ -3768,7 +3768,7 @@ buspirate led 1
@end deffn
@deffn {Interface Driver} {esp_usb_jtag}
Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB Bridge board using OpenOCD.
Espressif JTAG driver to communicate with ESP32-C3, ESP32-C6, ESP32-H2 and ESP32-S3 chips and ESP USB Bridge board using OpenOCD.
These chips have built-in JTAG circuitry and can be debugged without any additional hardware.
Only an USB cable connected to the D+/D- pins is necessary.
@@ -5146,6 +5146,10 @@ The current implementation supports eSi-32xx cores.
@item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
@item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{esp32c2} -- this is an Espressif SoC with single RISC-V core.
@item @code{esp32c3} -- this is an Espressif SoC with single RISC-V core.
@item @code{esp32c6} -- this is an Espressif SoC with single RISC-V core.
@item @code{esp32h2} -- this is an Espressif SoC with single RISC-V core.
@item @code{fa526} -- resembles arm920 (w/o Thumb).
@item @code{feroceon} -- resembles arm926.
@item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.