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tcl: add Espressif RISC-V config files

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Add configuration files for Espressif RISC-V based chips:
- ESP32-C2, ESP32-C3, ESP32-C6, ESP32-H2 target configs
- Board configs for builtin USB-JTAG and FTDI interfaces

while adding the new config files:
- Fix indentation in existing Espressif config files
- Adapt esp_common.cfg with RISC-V support
- Add explicit 'transport select jtag' to interface configs to avoid
  'DEPRECATED: auto-selecting transport' warning

Change-Id: I45fcbca2fe50888750e2e98a0a6773de86aad6d0
Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9195
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
2025-11-01 14:36:27 +01:00
committed by Antonio Borneo
parent 52ea420dd2
commit 04c6a6ee0e
17 changed files with 659 additions and 44 deletions
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66
tcl/target/esp_common.cfg
View File

@@ -6,6 +6,14 @@ source [find bitsbytes.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
# Riscv Debug Module Registers which are used around esp configuration files.
set _RISCV_ABS_DATA0 0x04
set _RISCV_DMCONTROL 0x10
set _RISCV_ABS_CMD 0x17
set _RISCV_SB_CS 0x38
set _RISCV_SB_ADDR0 0x39
set _RISCV_SB_DATA0 0x3C
# Common ESP chips definitions
# Espressif supports only NuttX in the upstream.
@@ -25,24 +33,31 @@ proc set_esp_common_variables { } {
global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1
global _ESP_WDT_DISABLE _ESP_SOC_RESET _ESP_MEMPROT_IS_ENABLED
global _TARGET_TYPE _ESP_ARCH
# For now we support dual core at most.
if { $_ONLYCPU == 1 && $_ESP_SMP_TARGET == 0} {
set _TARGETNAME_0 $_CHIPNAME
set _CPUNAME_0 cpu
set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0
set _TARGETNAME_0 $_CHIPNAME
set _CPUNAME_0 cpu
set _TAPNAME_0 $_CHIPNAME.$_CPUNAME_0
} else {
set _CPUNAME_0 cpu0
set _CPUNAME_1 cpu1
set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0
set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1
set _TAPNAME_0 $_TARGETNAME_0
set _TAPNAME_1 $_TARGETNAME_1
set _CPUNAME_0 cpu0
set _CPUNAME_1 cpu1
set _TARGETNAME_0 $_CHIPNAME.$_CPUNAME_0
set _TARGETNAME_1 $_CHIPNAME.$_CPUNAME_1
set _TAPNAME_0 $_TARGETNAME_0
set _TAPNAME_1 $_TARGETNAME_1
}
set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable"
set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset"
set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled"
if {$_ESP_ARCH == "riscv"} {
set _TARGET_TYPE $_ESP_ARCH
} else {
set _TARGET_TYPE $_CHIPNAME
}
set _ESP_WDT_DISABLE "${_CHIPNAME}_wdt_disable"
set _ESP_SOC_RESET "${_CHIPNAME}_soc_reset"
set _ESP_MEMPROT_IS_ENABLED "${_CHIPNAME}_memprot_is_enabled"
}
proc create_esp_jtag { } {
@@ -56,11 +71,11 @@ proc create_esp_jtag { } {
}
proc create_openocd_targets { } {
global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU
global _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1 _RTOS _CHIPNAME _ONLYCPU _TARGET_TYPE
target create $_TARGETNAME_0 $_CHIPNAME -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
target create $_TARGETNAME_0 $_TARGET_TYPE -chain-position $_TAPNAME_0 -coreid 0 -rtos $_RTOS
if { $_ONLYCPU != 1 } {
target create $_TARGETNAME_1 $_CHIPNAME -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
target create $_TARGETNAME_1 $_TARGET_TYPE -chain-position $_TAPNAME_1 -coreid 1 -rtos $_RTOS
target smp $_TARGETNAME_0 $_TARGETNAME_1
}
}
@@ -69,13 +84,12 @@ proc create_esp_target { ARCH } {
set_esp_common_variables
create_esp_jtag
create_openocd_targets
configure_openocd_events
configure_openocd_events $ARCH
if { $ARCH == "xtensa"} {
configure_esp_xtensa_default_settings
} else {
# riscv targets are not upstreamed yet.
# they can be found at the official Espressif fork.
configure_esp_riscv_default_settings
}
}
@@ -131,7 +145,6 @@ proc configure_event_halted { } {
$_TARGETNAME_0 configure -event halted {
global _ESP_WDT_DISABLE
$_ESP_WDT_DISABLE
esp halted_event_handler
}
}
@@ -167,12 +180,25 @@ proc configure_event_gdb_attach { } {
}
}
proc configure_openocd_events { } {
proc configure_openocd_events { ARCH } {
if { $ARCH == "riscv" } {
configure_event_halted
}
configure_event_examine_end
configure_event_reset_assert_post
configure_event_gdb_attach
}
proc configure_esp_riscv_default_settings { } {
gdb breakpoint_override hard
riscv set_reset_timeout_sec 2
riscv set_command_timeout_sec 5
riscv set_mem_access sysbus progbuf abstract
riscv set_ebreakm on
riscv set_ebreaks on
riscv set_ebreaku on
}
proc configure_esp_xtensa_default_settings { } {
global _TARGETNAME_0 _ESP_SMP_BREAK _FLASH_VOLTAGE _CHIPNAME