target: cortex-m: add support for armv8m caches

Cores like Cortex-M7, Cortex-M55 and Cortex-M85 can have either
D-Cache and/or I-Cache.
Using SW breakpoints in RAM requires handling these caches.

Detect the presence of cache at examine.
Detect cache state (enable/disable) at debug entry.
Take care of caches synchronization through the PoC (usually the
SRAM) while setting and removing SW breakpoints.
Add command 'cache_info' to check cache presence and size.

Change-Id: Ice637c215fe3042c8fff57edefbab1b86515ef4b
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9077
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins

src/target/Makefile.am

@@ -75,6 +75,7 @@ ARMV6_SRC = \
 
 ARMV7_SRC = \
 	%D%/armv7m.c \
+	%D%/armv7m_cache.c \
 	%D%/armv7m_trace.c \
 	%D%/cortex_m.c \
 	%D%/armv7a.c \
@@ -183,6 +184,7 @@ ARC_SRC = \
 	%D%/armv4_5_cache.h \
 	%D%/armv7a.h \
 	%D%/armv7m.h \
+	%D%/armv7m_cache.h \
 	%D%/armv7m_trace.h \
 	%D%/armv8.h \
 	%D%/armv8_dpm.h \