Fix crash when mode number fetched from the target is invalid.
git-svn-id: svn://svn.berlios.de/openocd/trunk@667 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@@ -903,6 +903,9 @@ int arm7_9_soft_reset_halt(struct target_s *target)
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armv4_5->core_mode = ARMV4_5_MODE_SVC;
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armv4_5->core_state = ARMV4_5_STATE_ARM;
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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/* reset registers */
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for (i = 0; i <= 14; i++)
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@@ -1091,6 +1094,8 @@ int arm7_9_debug_entry(target_t *target)
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LOG_ERROR("unknown debug reason: %i", target->debug_reason);
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}
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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for (i=0; i<=15; i++)
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{
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@@ -1101,6 +1106,9 @@ int arm7_9_debug_entry(target_t *target)
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}
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LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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/* exceptions other than USR & SYS have a saved program status register */
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if ((armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_USR) && (armv4_5_mode_to_number(armv4_5->core_mode) != ARMV4_5_MODE_SYS))
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@@ -1140,6 +1148,9 @@ int arm7_9_full_context(target_t *target)
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LOG_WARNING("target not halted");
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return ERROR_TARGET_NOT_HALTED;
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}
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
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* SYS shares registers with User, so we don't touch SYS
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@@ -1226,6 +1237,9 @@ int arm7_9_restore_context(target_t *target)
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if (arm7_9->pre_restore_context)
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arm7_9->pre_restore_context(target);
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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/* iterate through processor modes (User, FIQ, IRQ, SVC, ABT, UND)
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* SYS shares registers with User, so we don't touch SYS
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*/
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@@ -1635,6 +1649,10 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
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int retval;
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
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if ((num < 0) || (num > 16))
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@@ -1696,6 +1714,10 @@ int arm7_9_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mo
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u32 reg[16];
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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enum armv4_5_mode reg_mode = ((armv4_5_core_reg_t*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info)->mode;
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if ((num < 0) || (num > 16))
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@@ -1871,6 +1893,9 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
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break;
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}
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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for (i=0; i<=last_reg; i++)
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
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@@ -2038,6 +2063,9 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
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buf_set_u32(dbg_ctrl->value, EICE_DBG_CONTROL_DBGACK, 1, 1);
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embeddedice_store_reg(dbg_ctrl);
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if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
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return ERROR_FAIL;
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for (i=0; i<=last_reg; i++)
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ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
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