tcl: add config file for hpmicro devices and boards
- add board and device config files - add interface config file for hpmicro evk boards Change-Id: I8afb0b734b1064d71c4af3c118c7777d0ead9e6b Signed-off-by: Ryan QIAN <jianghao.qian@hpmicro.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8697 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Ryan QIAN
66
tcl/board/hpmicro/hpm5300evk.cfg
Normal file
66
tcl/board/hpmicro/hpm5300evk.cfg
Normal file
@@ -0,0 +1,66 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2023 HPMicro
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adapter speed 10000
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source [find interface/hpmicro/hpmicro_evk.cfg]
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source [find target/hpmicro/hpm5300.cfg]
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# openocd flash driver argument:
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# - option0:
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# [31:28] Flash probe type
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# 0 - SFDP SDR / 1 - SFDP DDR
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# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
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# 8 - Xccela DDR (SPI -> OPI DDR)
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# 10 - EcoXiP DDR (SPI -> OPI DDR)
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||||
# [27:24] Command Pads after Power-on Reset
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [23:20] Command Pads after Configuring FLASH
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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# 0 - Not needed
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# 1 - QE bit is at bit6 in Status Register 1
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# 2 - QE bit is at bit1 in Status Register 2
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# 3 - QE bit is at bit7 in Status Register 2
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# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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||||
# [15:8] Dummy cycles
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# 0 - Auto-probed / detected / default value
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# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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# [7:4] Misc.
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# 0 - Not used
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# 1 - SPI mode
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# 2 - Internal loopback
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# 3 - External DQS
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# [3:0] Frequency option
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# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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# - option1:
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||||
# [31:20] Reserved
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# [19:16] IO voltage
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# 0 - 3V / 1 - 1.8V
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# [15:12] Pin group
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# 0 - 1st group / 1 - 2nd group
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# [11:8] Connection selection
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# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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# [7:0] Drive Strength
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# 0 - Default value
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# xpi0 configs
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# - flash driver: hpm_xpi
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# - flash ctrl index: 0xF3000000
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# - base address: 0x80000000
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# - flash size: 0x2000000
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# - flash option0: 0x5
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# - flash option1: 0x1000
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flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x5 0x1000
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proc init_clock {} {
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mww 0xF4000800 0xFFFFFFFF
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mww 0xF4000810 0xFFFFFFFF
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mww 0xF4000820 0xFFFFFFFF
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mww 0xF4000830 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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$_TARGET0 configure -event reset-init {
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init_clock
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}
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66
tcl/board/hpmicro/hpm5301evklite.cfg
Normal file
66
tcl/board/hpmicro/hpm5301evklite.cfg
Normal file
@@ -0,0 +1,66 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2023 HPMicro
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adapter speed 10000
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source [find interface/hpmicro/hpmicro_evk.cfg]
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source [find target/hpmicro/hpm5300.cfg]
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# openocd flash driver argument:
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||||
# - option0:
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||||
# [31:28] Flash probe type
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||||
# 0 - SFDP SDR / 1 - SFDP DDR
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||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
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# 8 - Xccela DDR (SPI -> OPI DDR)
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||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
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||||
# [27:24] Command Pads after Power-on Reset
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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||||
# [23:20] Command Pads after Configuring FLASH
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||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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||||
# 0 - Not needed
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||||
# 1 - QE bit is at bit6 in Status Register 1
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||||
# 2 - QE bit is at bit1 in Status Register 2
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||||
# 3 - QE bit is at bit7 in Status Register 2
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||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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||||
# [15:8] Dummy cycles
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||||
# 0 - Auto-probed / detected / default value
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||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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# [7:4] Misc.
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# 0 - Not used
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# 1 - SPI mode
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# 2 - Internal loopback
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# 3 - External DQS
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# [3:0] Frequency option
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# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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# - option1:
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# [31:20] Reserved
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# [19:16] IO voltage
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# 0 - 3V / 1 - 1.8V
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||||
# [15:12] Pin group
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# 0 - 1st group / 1 - 2nd group
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# [11:8] Connection selection
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# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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# [7:0] Drive Strength
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# 0 - Default value
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# xpi0 configs
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# - flash driver: hpm_xpi
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# - flash ctrl index: 0xF3000000
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# - base address: 0x80000000
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# - flash size: 0x2000000
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# - flash option0: 0x5
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# - flash option1: 0x1000
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flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
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proc init_clock {} {
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mww 0xF4000800 0xFFFFFFFF
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mww 0xF4000810 0xFFFFFFFF
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mww 0xF4000820 0xFFFFFFFF
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mww 0xF4000830 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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$_TARGET0 configure -event reset-init {
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init_clock
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}
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64
tcl/board/hpmicro/hpm6200evk.cfg
Normal file
64
tcl/board/hpmicro/hpm6200evk.cfg
Normal file
@@ -0,0 +1,64 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2023 HPMicro
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adapter speed 10000
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source [find interface/hpmicro/hpmicro_evk.cfg]
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source [find target/hpmicro/hpm6280-single-core.cfg]
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# openocd flash driver argument:
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||||
# - option0:
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||||
# [31:28] Flash probe type
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||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
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||||
# [31:20] Reserved
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||||
# [19:16] IO voltage
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||||
# 0 - 3V / 1 - 1.8V
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||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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||||
# [7:0] Drive Strength
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||||
# 0 - Default value
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||||
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||||
# xpi0 configs
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# - flash driver: hpm_xpi
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# - flash ctrl index: 0xF3040000
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# - base address: 0x80000000
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# - flash size: 0x1000000
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flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
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proc init_clock {} {
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mww 0xF4000800 0xFFFFFFFF
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mww 0xF4000810 0xFFFFFFFF
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mww 0xF4000820 0xFFFFFFFF
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mww 0xF4000830 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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||||
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$_TARGET0 configure -event reset-init {
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init_clock
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}
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||||
217
tcl/board/hpmicro/hpm6300evk.cfg
Normal file
217
tcl/board/hpmicro/hpm6300evk.cfg
Normal file
@@ -0,0 +1,217 @@
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2021 HPMicro
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adapter speed 10000
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source [find interface/hpmicro/hpmicro_evk.cfg]
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source [find target/hpmicro/hpm6360.cfg]
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# openocd flash driver argument:
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||||
# - option0:
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||||
# [31:28] Flash probe type
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||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3040000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x1000000
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
|
||||
|
||||
proc init_clock {} {
|
||||
mww 0xF4000800 0xFFFFFFFF
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||||
mww 0xF4000810 0xFFFFFFFF
|
||||
mww 0xF4000820 0xFFFFFFFF
|
||||
mww 0xF4000830 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
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||||
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||||
proc init_sdram { } {
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# configure femc frequency
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# 166Mhz pll0_clk1: 333Mhz divide by 2
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mww 0xF4001808 0x201
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# PA25
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mww 0xF40400C8 0xC
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# PA26
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mww 0xF40400D0 0xC
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# PA27
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mww 0xF40400D8 0xC
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# PA28
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mww 0xF40400E0 0xC
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# PA29
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||||
mww 0xF40400E8 0xC
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# PA30
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||||
mww 0xF40400F0 0xC
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||||
# PA31
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mww 0xF40400F8 0xC
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# PB00
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||||
mww 0xF4040100 0xC
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# PB01
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mww 0xF4040108 0xC
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# PB02
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mww 0xF4040110 0xC
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||||
# PB03
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mww 0xF4040118 0xC
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||||
# PB04
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||||
mww 0xF4040120 0xC
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||||
# PB05
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||||
mww 0xF4040128 0xC
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||||
# PB06
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mww 0xF4040130 0xC
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||||
# PB07
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mww 0xF4040138 0xC
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||||
# PB08
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mww 0xF4040140 0xC
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||||
# PB09
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||||
mww 0xF4040148 0xC
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||||
# PB10
|
||||
mww 0xF4040150 0xC
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||||
# PB11
|
||||
mww 0xF4040158 0xC
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||||
# PB12
|
||||
mww 0xF4040160 0xC
|
||||
# PB13
|
||||
mww 0xF4040168 0xC
|
||||
# PB14
|
||||
mww 0xF4040170 0xC
|
||||
# PB15
|
||||
mww 0xF4040178 0xC
|
||||
# PB16
|
||||
mww 0xF4040180 0xC
|
||||
# PB17
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||||
mww 0xF4040188 0xC
|
||||
# PB18
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||||
mww 0xF4040190 0xC
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||||
# PB19
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||||
mww 0xF4040198 0xC
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||||
# PB20
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||||
mww 0xF40401A0 0xC
|
||||
|
||||
# PB21
|
||||
mww 0xF40401A8 0xC
|
||||
# PB22
|
||||
mww 0xF40401B0 0xC
|
||||
# PB23
|
||||
mww 0xF40401B8 0xC
|
||||
# PB24
|
||||
mww 0xF40401C0 0xC
|
||||
# PB25
|
||||
mww 0xF40401C8 0xC
|
||||
# PB26
|
||||
mww 0xF40401D0 0xC
|
||||
# PB27
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||||
mww 0xF40401D8 0xC
|
||||
# PB28
|
||||
mww 0xF40401E0 0xC
|
||||
# PB29
|
||||
mww 0xF40401E8 0xC
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||||
# PB30
|
||||
mww 0xF40401F0 0xC
|
||||
# PB31
|
||||
mww 0xF40401F8 0xC
|
||||
|
||||
# femc configuration
|
||||
mww 0xF3050000 0x1
|
||||
sleep 10
|
||||
mww 0xF3050000 0x2
|
||||
mww 0xF3050008 0x30524
|
||||
mww 0xF305000C 0x6030524
|
||||
mww 0xF3050000 0x10000004
|
||||
|
||||
# 32MB
|
||||
mww 0xF3050010 0x4000001b
|
||||
mww 0xF3050014 0
|
||||
# 16-bit
|
||||
mww 0xF3050040 0xf31
|
||||
|
||||
# 166Mhz configuration
|
||||
mww 0xF3050044 0x884e33
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF305004C 0x2020300
|
||||
|
||||
# config delay cell
|
||||
mww 0xF3050150 0x2000
|
||||
mww 0xF3050094 0
|
||||
mww 0xF3050098 0
|
||||
|
||||
# precharge all
|
||||
mww 0xF3050090 0x40000000
|
||||
mww 0xF305009C 0xA55A000F
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
# auto refresh
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
|
||||
# set mode
|
||||
mww 0xF30500A0 0x33
|
||||
mww 0xF305009C 0xA55A000A
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305004C 0x2020301
|
||||
echo "SDRAM has been initialized"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
init_sdram
|
||||
}
|
||||
239
tcl/board/hpmicro/hpm6750evk.cfg
Normal file
239
tcl/board/hpmicro/hpm6750evk.cfg
Normal file
@@ -0,0 +1,239 @@
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright (c) 2021 HPMicro
|
||||
|
||||
adapter speed 10000
|
||||
source [find interface/hpmicro/hpmicro_evk.cfg]
|
||||
source [find target/hpmicro/hpm6750-single-core.cfg]
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3040000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3040000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
mww 0xF4000800 0xFFFFFFFF
|
||||
mww 0xF4000810 0xFFFFFFFF
|
||||
mww 0xF4000820 0xFFFFFFFF
|
||||
mww 0xF4000830 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
proc init_sdram { } {
|
||||
# configure femc frequency
|
||||
# 133Mhz pll1_clk0: 266Mhz divide by 2
|
||||
#mww 0xF4001820 0x201
|
||||
# 166Mhz pll2_clk0: 333Mhz divide by 2
|
||||
mww 0xF4001820 0x401
|
||||
# PC01
|
||||
mww 0xF4040208 0xC
|
||||
# PC00
|
||||
mww 0xF4040200 0xC
|
||||
# PB31
|
||||
mww 0xF40401F8 0xC
|
||||
# PB30
|
||||
mww 0xF40401F0 0xC
|
||||
# PB29
|
||||
mww 0xF40401E8 0xC
|
||||
# PB28
|
||||
mww 0xF40401E0 0xC
|
||||
# PB27
|
||||
mww 0xF40401D8 0xC
|
||||
# PB26
|
||||
mww 0xF40401D0 0xC
|
||||
# PB25
|
||||
mww 0xF40401C8 0xC
|
||||
# PB24
|
||||
mww 0xF40401C0 0xC
|
||||
# PB23
|
||||
mww 0xF40401B8 0xC
|
||||
# PB22
|
||||
mww 0xF40401B0 0xC
|
||||
# PB21
|
||||
mww 0xF40401A8 0xC
|
||||
# PB20
|
||||
mww 0xF40401A0 0xC
|
||||
# PB19
|
||||
mww 0xF4040198 0xC
|
||||
# PB18
|
||||
mww 0xF4040190 0xC
|
||||
|
||||
# PD13
|
||||
mww 0xF4040368 0xC
|
||||
# PD12
|
||||
mww 0xF4040360 0xC
|
||||
# PD10
|
||||
mww 0xF4040350 0xC
|
||||
# PD09
|
||||
mww 0xF4040348 0xC
|
||||
# PD08
|
||||
mww 0xF4040340 0xC
|
||||
# PD07
|
||||
mww 0xF4040338 0xC
|
||||
# PD06
|
||||
mww 0xF4040330 0xC
|
||||
# PD05
|
||||
mww 0xF4040328 0xC
|
||||
# PD04
|
||||
mww 0xF4040320 0xC
|
||||
# PD03
|
||||
mww 0xF4040318 0xC
|
||||
# PD02
|
||||
mww 0xF4040310 0xC
|
||||
# PD01
|
||||
mww 0xF4040308 0xC
|
||||
# PD00
|
||||
mww 0xF4040300 0xC
|
||||
# PC29
|
||||
mww 0xF40402E8 0xC
|
||||
# PC28
|
||||
mww 0xF40402E0 0xC
|
||||
# PC27
|
||||
mww 0xF40402D8 0xC
|
||||
|
||||
# PC22
|
||||
mww 0xF40402B0 0xC
|
||||
# PC21
|
||||
mww 0xF40402A8 0xC
|
||||
# PC17
|
||||
mww 0xF4040288 0xC
|
||||
# PC15
|
||||
mww 0xF4040278 0xC
|
||||
# PC12
|
||||
mww 0xF4040260 0xC
|
||||
# PC11
|
||||
mww 0xF4040258 0xC
|
||||
# PC10
|
||||
mww 0xF4040250 0xC
|
||||
# PC09
|
||||
mww 0xF4040248 0xC
|
||||
# PC08
|
||||
mww 0xF4040240 0xC
|
||||
# PC07
|
||||
mww 0xF4040238 0xC
|
||||
# PC06
|
||||
mww 0xF4040230 0xC
|
||||
# PC05
|
||||
mww 0xF4040228 0xC
|
||||
# PC04
|
||||
mww 0xF4040220 0xC
|
||||
|
||||
# PC14
|
||||
mww 0xF4040270 0xC
|
||||
# PC13
|
||||
mww 0xF4040268 0xC
|
||||
# PC16
|
||||
# mww 0xF4040280 0x1000C
|
||||
# PC26
|
||||
mww 0xF40402D0 0xC
|
||||
# PC25
|
||||
mww 0xF40402C8 0xC
|
||||
# PC19
|
||||
mww 0xF4040298 0xC
|
||||
# PC18
|
||||
mww 0xF4040290 0xC
|
||||
# PC23
|
||||
mww 0xF40402B8 0xC
|
||||
# PC24
|
||||
mww 0xF40402C0 0xC
|
||||
# PC30
|
||||
mww 0xF40402F0 0xC
|
||||
# PC31
|
||||
mww 0xF40402F8 0xC
|
||||
# PC02
|
||||
mww 0xF4040210 0xC
|
||||
# PC03
|
||||
mww 0xF4040218 0xC
|
||||
|
||||
# femc configuration
|
||||
mww 0xF3050000 0x1
|
||||
sleep 10
|
||||
mww 0xF3050000 0x2
|
||||
mww 0xF3050008 0x30524
|
||||
mww 0xF305000C 0x6030524
|
||||
mww 0xF3050000 0x10000000
|
||||
mww 0xF3050010 0x4000001b
|
||||
mww 0xF3050014 0
|
||||
mww 0xF3050040 0xf32
|
||||
|
||||
# 133Mhz configuration
|
||||
#mww 0xF3050044 0x884e22
|
||||
# 166Mhz configuration
|
||||
mww 0xF3050044 0x884e33
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF305004C 0x2020300
|
||||
|
||||
# config delay cell
|
||||
mww 0xF3050150 0x3b
|
||||
mww 0xF3050150 0x203b
|
||||
mww 0xF3050094 0
|
||||
mww 0xF3050098 0
|
||||
|
||||
# precharge all
|
||||
mww 0xF3050090 0x40000000
|
||||
mww 0xF305009C 0xA55A000F
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
# auto refresh
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
|
||||
# set mode
|
||||
mww 0xF30500A0 0x33
|
||||
mww 0xF305009C 0xA55A000A
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305004C 0x2020301
|
||||
echo "SDRAM has been initialized"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
init_sdram
|
||||
}
|
||||
239
tcl/board/hpmicro/hpm6750evk2.cfg
Normal file
239
tcl/board/hpmicro/hpm6750evk2.cfg
Normal file
@@ -0,0 +1,239 @@
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright (c) 2022 HPMicro
|
||||
|
||||
adapter speed 10000
|
||||
source [find interface/hpmicro/hpmicro_evk.cfg]
|
||||
source [find target/hpmicro/hpm6750-single-core.cfg]
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3040000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
mww 0xF4000800 0xFFFFFFFF
|
||||
mww 0xF4000810 0xFFFFFFFF
|
||||
mww 0xF4000820 0xFFFFFFFF
|
||||
mww 0xF4000830 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
proc init_sdram { } {
|
||||
# configure femc frequency
|
||||
# 133Mhz pll1_clk0: 266Mhz divide by 2
|
||||
#mww 0xF4001820 0x201
|
||||
# 166Mhz pll2_clk0: 333Mhz divide by 2
|
||||
mww 0xF4001820 0x401
|
||||
# PC01
|
||||
mww 0xF4040208 0xC
|
||||
# PC00
|
||||
mww 0xF4040200 0xC
|
||||
# PB31
|
||||
mww 0xF40401F8 0xC
|
||||
# PB30
|
||||
mww 0xF40401F0 0xC
|
||||
# PB29
|
||||
mww 0xF40401E8 0xC
|
||||
# PB28
|
||||
mww 0xF40401E0 0xC
|
||||
# PB27
|
||||
mww 0xF40401D8 0xC
|
||||
# PB26
|
||||
mww 0xF40401D0 0xC
|
||||
# PB25
|
||||
mww 0xF40401C8 0xC
|
||||
# PB24
|
||||
mww 0xF40401C0 0xC
|
||||
# PB23
|
||||
mww 0xF40401B8 0xC
|
||||
# PB22
|
||||
mww 0xF40401B0 0xC
|
||||
# PB21
|
||||
mww 0xF40401A8 0xC
|
||||
# PB20
|
||||
mww 0xF40401A0 0xC
|
||||
# PB19
|
||||
mww 0xF4040198 0xC
|
||||
# PB18
|
||||
mww 0xF4040190 0xC
|
||||
|
||||
# PD13
|
||||
mww 0xF4040368 0xC
|
||||
# PD12
|
||||
mww 0xF4040360 0xC
|
||||
# PD10
|
||||
mww 0xF4040350 0xC
|
||||
# PD09
|
||||
mww 0xF4040348 0xC
|
||||
# PD08
|
||||
mww 0xF4040340 0xC
|
||||
# PD07
|
||||
mww 0xF4040338 0xC
|
||||
# PD06
|
||||
mww 0xF4040330 0xC
|
||||
# PD05
|
||||
mww 0xF4040328 0xC
|
||||
# PD04
|
||||
mww 0xF4040320 0xC
|
||||
# PD03
|
||||
mww 0xF4040318 0xC
|
||||
# PD02
|
||||
mww 0xF4040310 0xC
|
||||
# PD01
|
||||
mww 0xF4040308 0xC
|
||||
# PD00
|
||||
mww 0xF4040300 0xC
|
||||
# PC29
|
||||
mww 0xF40402E8 0xC
|
||||
# PC28
|
||||
mww 0xF40402E0 0xC
|
||||
# PC27
|
||||
mww 0xF40402D8 0xC
|
||||
|
||||
# PC22
|
||||
mww 0xF40402B0 0xC
|
||||
# PC21
|
||||
mww 0xF40402A8 0xC
|
||||
# PC17
|
||||
mww 0xF4040288 0xC
|
||||
# PC15
|
||||
mww 0xF4040278 0xC
|
||||
# PC12
|
||||
mww 0xF4040260 0xC
|
||||
# PC11
|
||||
mww 0xF4040258 0xC
|
||||
# PC10
|
||||
mww 0xF4040250 0xC
|
||||
# PC09
|
||||
mww 0xF4040248 0xC
|
||||
# PC08
|
||||
mww 0xF4040240 0xC
|
||||
# PC07
|
||||
mww 0xF4040238 0xC
|
||||
# PC06
|
||||
mww 0xF4040230 0xC
|
||||
# PC05
|
||||
mww 0xF4040228 0xC
|
||||
# PC04
|
||||
mww 0xF4040220 0xC
|
||||
|
||||
# PC14
|
||||
mww 0xF4040270 0xC
|
||||
# PC13
|
||||
mww 0xF4040268 0xC
|
||||
# PC16
|
||||
#mww 0xF4040280 0x1000C
|
||||
# PC26
|
||||
mww 0xF40402D0 0xC
|
||||
# PC25
|
||||
mww 0xF40402C8 0xC
|
||||
# PC19
|
||||
mww 0xF4040298 0xC
|
||||
# PC18
|
||||
mww 0xF4040290 0xC
|
||||
# PC23
|
||||
mww 0xF40402B8 0xC
|
||||
# PC24
|
||||
mww 0xF40402C0 0xC
|
||||
# PC30
|
||||
mww 0xF40402F0 0xC
|
||||
# PC31
|
||||
mww 0xF40402F8 0xC
|
||||
# PC02
|
||||
mww 0xF4040210 0xC
|
||||
# PC03
|
||||
mww 0xF4040218 0xC
|
||||
|
||||
# femc configuration
|
||||
mww 0xF3050000 0x1
|
||||
sleep 10
|
||||
mww 0xF3050000 0x2
|
||||
mww 0xF3050008 0x30524
|
||||
mww 0xF305000C 0x6030524
|
||||
mww 0xF3050000 0x10000000
|
||||
mww 0xF3050010 0x4000001b
|
||||
mww 0xF3050014 0
|
||||
mww 0xF3050040 0xf32
|
||||
|
||||
# 133Mhz configuration
|
||||
#mww 0xF3050044 0x884e22
|
||||
# 166Mhz configuration
|
||||
mww 0xF3050044 0x884e33
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF305004C 0x2020300
|
||||
|
||||
# config delay cell
|
||||
mww 0xF3050150 0x3b
|
||||
mww 0xF3050150 0x203b
|
||||
mww 0xF3050094 0
|
||||
mww 0xF3050098 0
|
||||
|
||||
# precharge all
|
||||
mww 0xF3050090 0x40000000
|
||||
mww 0xF305009C 0xA55A000F
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
# auto refresh
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
|
||||
# set mode
|
||||
mww 0xF30500A0 0x33
|
||||
mww 0xF305009C 0xA55A000A
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305004C 0x2020301
|
||||
echo "SDRAM has been initialized"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
init_sdram
|
||||
}
|
||||
210
tcl/board/hpmicro/hpm6750evkmini.cfg
Normal file
210
tcl/board/hpmicro/hpm6750evkmini.cfg
Normal file
@@ -0,0 +1,210 @@
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright (c) 2021 HPMicro
|
||||
|
||||
adapter speed 10000
|
||||
source [find interface/hpmicro/hpmicro_evk.cfg]
|
||||
source [find target/hpmicro/hpm6750-single-core.cfg]
|
||||
# openocd flash driver argument:
|
||||
# - ARG7:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - ARG8:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3040000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x1000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
mww 0xF4000800 0xFFFFFFFF
|
||||
mww 0xF4000810 0xFFFFFFFF
|
||||
mww 0xF4000820 0xFFFFFFFF
|
||||
mww 0xF4000830 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
proc init_sdram { } {
|
||||
# configure femc frequency
|
||||
# 133Mhz pll1_clk0: 266Mhz divide by 2
|
||||
#mww 0xF4001820 0x201
|
||||
# 166Mhz pll2_clk0: 333Mhz divide by 2
|
||||
mww 0xF4001820 0x401
|
||||
|
||||
# PD13
|
||||
mww 0xF4040368 0xC
|
||||
# PD12
|
||||
mww 0xF4040360 0xC
|
||||
# PD10
|
||||
mww 0xF4040350 0xC
|
||||
# PD09
|
||||
mww 0xF4040348 0xC
|
||||
# PD08
|
||||
mww 0xF4040340 0xC
|
||||
# PD07
|
||||
mww 0xF4040338 0xC
|
||||
# PD06
|
||||
mww 0xF4040330 0xC
|
||||
# PD05
|
||||
mww 0xF4040328 0xC
|
||||
# PD04
|
||||
mww 0xF4040320 0xC
|
||||
# PD03
|
||||
mww 0xF4040318 0xC
|
||||
# PD02
|
||||
mww 0xF4040310 0xC
|
||||
# PD01
|
||||
mww 0xF4040308 0xC
|
||||
# PD00
|
||||
mww 0xF4040300 0xC
|
||||
# PC29
|
||||
mww 0xF40402E8 0xC
|
||||
# PC28
|
||||
mww 0xF40402E0 0xC
|
||||
# PC27
|
||||
mww 0xF40402D8 0xC
|
||||
|
||||
# PC22
|
||||
mww 0xF40402B0 0xC
|
||||
# PC21
|
||||
mww 0xF40402A8 0xC
|
||||
# PC17
|
||||
mww 0xF4040288 0xC
|
||||
# PC15
|
||||
mww 0xF4040278 0xC
|
||||
# PC12
|
||||
mww 0xF4040260 0xC
|
||||
# PC11
|
||||
mww 0xF4040258 0xC
|
||||
# PC10
|
||||
mww 0xF4040250 0xC
|
||||
# PC09
|
||||
mww 0xF4040248 0xC
|
||||
# PC08
|
||||
mww 0xF4040240 0xC
|
||||
# PC07
|
||||
mww 0xF4040238 0xC
|
||||
# PC06
|
||||
mww 0xF4040230 0xC
|
||||
# PC05
|
||||
mww 0xF4040228 0xC
|
||||
# PC04
|
||||
mww 0xF4040220 0xC
|
||||
|
||||
# PC14
|
||||
mww 0xF4040270 0xC
|
||||
# PC13
|
||||
mww 0xF4040268 0xC
|
||||
# PC16
|
||||
#mww 0xF4040280 0x1000C
|
||||
# PC26
|
||||
mww 0xF40402D0 0xC
|
||||
# PC25
|
||||
mww 0xF40402C8 0xC
|
||||
# PC19
|
||||
mww 0xF4040298 0xC
|
||||
# PC18
|
||||
mww 0xF4040290 0xC
|
||||
# PC23
|
||||
mww 0xF40402B8 0xC
|
||||
# PC24
|
||||
mww 0xF40402C0 0xC
|
||||
# PC30
|
||||
mww 0xF40402F0 0xC
|
||||
# PC31
|
||||
mww 0xF40402F8 0xC
|
||||
# PC02
|
||||
mww 0xF4040210 0xC
|
||||
# PC03
|
||||
mww 0xF4040218 0xC
|
||||
|
||||
# femc configuration
|
||||
mww 0xF3050000 0x1
|
||||
sleep 10
|
||||
mww 0xF3050000 0x2
|
||||
mww 0xF3050008 0x30524
|
||||
mww 0xF305000C 0x6030524
|
||||
mww 0xF3050000 0x10000000
|
||||
|
||||
# 16MB
|
||||
mww 0xF3050010 0x40000019
|
||||
mww 0xF3050014 0
|
||||
# 16-bit
|
||||
mww 0xF3050040 0xf31
|
||||
|
||||
# 133Mhz configuration
|
||||
#mww 0xF3050044 0x884e22
|
||||
# 166Mhz configuration
|
||||
mww 0xF3050044 0x884e33
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF3050048 0x1020d0d
|
||||
mww 0xF305004C 0x2020300
|
||||
|
||||
# config delay cell
|
||||
mww 0xF3050150 0x3b
|
||||
mww 0xF3050150 0x203b
|
||||
mww 0xF3050094 0
|
||||
mww 0xF3050098 0
|
||||
|
||||
# precharge all
|
||||
mww 0xF3050090 0x40000000
|
||||
mww 0xF305009C 0xA55A000F
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
# auto refresh
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305009C 0xA55A000C
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
|
||||
# set mode
|
||||
mww 0xF30500A0 0x33
|
||||
mww 0xF305009C 0xA55A000A
|
||||
sleep 500
|
||||
mww 0xF305003C 0x3
|
||||
mww 0xF305004C 0x2020301
|
||||
echo "SDRAM has been initialized"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
init_sdram
|
||||
}
|
||||
157
tcl/board/hpmicro/hpm6800evk.cfg
Normal file
157
tcl/board/hpmicro/hpm6800evk.cfg
Normal file
@@ -0,0 +1,157 @@
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright (c) 2023 HPMicro
|
||||
|
||||
adapter speed 10000
|
||||
source [find interface/hpmicro/hpmicro_evk.cfg]
|
||||
source [find target/hpmicro/hpm6880.cfg]
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3000000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
mww 0xF4000800 0xFFFFFFFF
|
||||
mww 0xF4000810 0xFFFFFFFF
|
||||
mww 0xF4000820 0xFFFFFFFF
|
||||
mww 0xF4000830 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
proc init_ddr3 {} {
|
||||
# ddr dcdc setup
|
||||
mww 0xF4104080 0x10578
|
||||
|
||||
# ddr3 setup
|
||||
mww 0xF40C0180 0x30000019
|
||||
mww 0xF400180C 0x09100401
|
||||
mww 0xF4153000 0xF0000010
|
||||
mww 0xF30101B0 0
|
||||
mww 0xF4150040 0xf004641f
|
||||
mww 0xF4153000 0xf0000011
|
||||
mww 0xF3013000 0xf4000000
|
||||
mww 0xF3010490 1
|
||||
mww 0xF3010000 0x1040001
|
||||
mww 0xF30100D0 0x4002004e
|
||||
mww 0xF3010110 0x05010407
|
||||
mww 0xF3010190 0x07040102
|
||||
mww 0xF3010194 0x20404
|
||||
mww 0xF30101A4 0x20008
|
||||
mww 0xF3010240 0x06000600
|
||||
mww 0xF3010200 0x1F1F1F
|
||||
mww 0xF3010204 0x121212
|
||||
mww 0xF3010208 0
|
||||
mww 0xF301020C 0
|
||||
mww 0xF3010210 0x1F1F
|
||||
mww 0xF3010214 0x06030303
|
||||
mww 0xF3010218 0x0F060606
|
||||
mww 0xF3013000 0xFC000000
|
||||
mww 0xF4150054 0xc70
|
||||
mww 0xF4150058 0x6
|
||||
mww 0xF415005c 0x18
|
||||
mww 0xF4150048 0x919c8866
|
||||
mww 0xF415004c 0x1a838360
|
||||
mww 0xF415008c 0xf06d50
|
||||
mww 0xF4150050 0x3002d200
|
||||
mww 0xF30101b0 1
|
||||
sleep 100
|
||||
mww 0xF4150068 0x930035C7
|
||||
mww 0xF4150004 0xFF81
|
||||
sleep 200
|
||||
echo "ddr3 has been enabled!"
|
||||
}
|
||||
|
||||
proc init_dram {} {
|
||||
# ddr dcdc setup
|
||||
mww 0xF4104080 0x10708
|
||||
|
||||
# pll1 setup
|
||||
mww 0xF40c0180 0xb0000016
|
||||
mww 0xF40c0184 0
|
||||
mww 0xF40c0188 0xe4e1c00
|
||||
|
||||
#ddr setup
|
||||
mww 0xF3010000 0x3040000
|
||||
mww 0xF30101B0 0
|
||||
mww 0xF4150044 0x40a
|
||||
mww 0xF4150040 0xf004641f
|
||||
mww 0xF4153000 0xf0000011
|
||||
mww 0xF3013000 0xf4000000
|
||||
mww 0xF3010490 1
|
||||
mww 0xF3010000 0x1040000
|
||||
mww 0xF3010190 0x07010101
|
||||
mww 0xF3010194 0x20404
|
||||
mww 0xF30101A4 0x20008
|
||||
mww 0xF3010240 0x6000600
|
||||
mww 0xF3010200 0x1f1f1f
|
||||
mww 0xF3010204 0x70707
|
||||
mww 0xF3010208 0
|
||||
mww 0xF301020c 0
|
||||
mww 0xF3010210 0x1f1f
|
||||
mww 0xF3010214 0x6060606
|
||||
mww 0xF3010218 0xf0f0606
|
||||
mww 0xF3013000 0xfc000000
|
||||
mww 0xF4150020 0x3000100
|
||||
mww 0xF4150028 0x18002356
|
||||
mww 0xF415002c 0x0aac4156
|
||||
mww 0xF4150054 0xe73
|
||||
mww 0xF4150058 0x5
|
||||
mww 0xF415005c 0
|
||||
mww 0xF4150048 0xf2adfe53
|
||||
mww 0xF415004c 0x22820362
|
||||
mww 0xF4150050 0x30020100
|
||||
mww 0xF415008c 0xf06d50
|
||||
mww 0xF30101b0 1
|
||||
sleep 100
|
||||
mww 0xF4150068 0x91003587
|
||||
mww 0xF4150004 0xF501
|
||||
sleep 200
|
||||
echo "ddr has been enabled!"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
init_ddr3
|
||||
}
|
||||
65
tcl/board/hpmicro/hpm6e00evk.cfg
Normal file
65
tcl/board/hpmicro/hpm6e00evk.cfg
Normal file
@@ -0,0 +1,65 @@
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# Copyright (c) 2024 HPMicro
|
||||
|
||||
adapter speed 10000
|
||||
source [find interface/hpmicro/hpmicro_evk.cfg]
|
||||
source [find target/hpmicro/hpm6e80-single-core.cfg]
|
||||
# openocd flash driver argument:
|
||||
# - option0:
|
||||
# [31:28] Flash probe type
|
||||
# 0 - SFDP SDR / 1 - SFDP DDR
|
||||
# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
|
||||
# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
|
||||
# 6 - OctaBus DDR (SPI -> OPI DDR)
|
||||
# 8 - Xccela DDR (SPI -> OPI DDR)
|
||||
# 10 - EcoXiP DDR (SPI -> OPI DDR)
|
||||
# [27:24] Command Pads after Power-on Reset
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [23:20] Command Pads after Configuring FLASH
|
||||
# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
|
||||
# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
|
||||
# 0 - Not needed
|
||||
# 1 - QE bit is at bit6 in Status Register 1
|
||||
# 2 - QE bit is at bit1 in Status Register 2
|
||||
# 3 - QE bit is at bit7 in Status Register 2
|
||||
# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
|
||||
# [15:8] Dummy cycles
|
||||
# 0 - Auto-probed / detected / default value
|
||||
# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
|
||||
# [7:4] Misc.
|
||||
# 0 - Not used
|
||||
# 1 - SPI mode
|
||||
# 2 - Internal loopback
|
||||
# 3 - External DQS
|
||||
# [3:0] Frequency option
|
||||
# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
|
||||
# - option1:
|
||||
# [31:20] Reserved
|
||||
# [19:16] IO voltage
|
||||
# 0 - 3V / 1 - 1.8V
|
||||
# [15:12] Pin group
|
||||
# 0 - 1st group / 1 - 2nd group
|
||||
# [11:8] Connection selection
|
||||
# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
|
||||
# [7:0] Drive Strength
|
||||
# 0 - Default value
|
||||
|
||||
# xpi0 configs
|
||||
# - flash driver: hpm_xpi
|
||||
# - flash ctrl index: 0xF3000000
|
||||
# - base address: 0x80000000
|
||||
# - flash size: 0x2000000
|
||||
# - flash option0: 0x7
|
||||
flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
|
||||
|
||||
proc init_clock {} {
|
||||
mww 0xF4000800 0xFFFFFFFF
|
||||
mww 0xF4000810 0xFFFFFFFF
|
||||
mww 0xF4000820 0xFFFFFFFF
|
||||
mww 0xF4000830 0xFFFFFFFF
|
||||
echo "clocks has been enabled!"
|
||||
}
|
||||
|
||||
$_TARGET0 configure -event reset-init {
|
||||
init_clock
|
||||
}
|
||||
Reference in New Issue
Block a user