tcl: add config file for hpmicro devices and boards
- add board and device config files - add interface config file for hpmicro evk boards Change-Id: I8afb0b734b1064d71c4af3c118c7777d0ead9e6b Signed-off-by: Ryan QIAN <jianghao.qian@hpmicro.com> Reviewed-on: https://review.openocd.org/c/openocd/+/8697 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Ryan QIAN
217
tcl/board/hpmicro/hpm6300evk.cfg
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217
tcl/board/hpmicro/hpm6300evk.cfg
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright (c) 2021 HPMicro
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adapter speed 10000
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source [find interface/hpmicro/hpmicro_evk.cfg]
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source [find target/hpmicro/hpm6360.cfg]
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# openocd flash driver argument:
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# - option0:
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# [31:28] Flash probe type
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# 0 - SFDP SDR / 1 - SFDP DDR
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# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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# 6 - OctaBus DDR (SPI -> OPI DDR)
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# 8 - Xccela DDR (SPI -> OPI DDR)
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# 10 - EcoXiP DDR (SPI -> OPI DDR)
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# [27:24] Command Pads after Power-on Reset
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [23:20] Command Pads after Configuring FLASH
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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# 0 - Not needed
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# 1 - QE bit is at bit6 in Status Register 1
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# 2 - QE bit is at bit1 in Status Register 2
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# 3 - QE bit is at bit7 in Status Register 2
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# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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# openocd flash driver argument:
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# - option0:
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# [31:28] Flash probe type
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# 0 - SFDP SDR / 1 - SFDP DDR
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# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
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# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
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# 6 - OctaBus DDR (SPI -> OPI DDR)
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# 8 - Xccela DDR (SPI -> OPI DDR)
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# 10 - EcoXiP DDR (SPI -> OPI DDR)
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# [27:24] Command Pads after Power-on Reset
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [23:20] Command Pads after Configuring FLASH
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# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
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# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
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# 0 - Not needed
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# 1 - QE bit is at bit6 in Status Register 1
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# 2 - QE bit is at bit1 in Status Register 2
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# 3 - QE bit is at bit7 in Status Register 2
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# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
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# [15:8] Dummy cycles
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# 0 - Auto-probed / detected / default value
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# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
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# [7:4] Misc.
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# 0 - Not used
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# 1 - SPI mode
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# 2 - Internal loopback
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# 3 - External DQS
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# [3:0] Frequency option
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# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
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# - option1:
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# [31:20] Reserved
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# [19:16] IO voltage
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# 0 - 3V / 1 - 1.8V
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# [15:12] Pin group
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# 0 - 1st group / 1 - 2nd group
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# [11:8] Connection selection
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# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
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# [7:0] Drive Strength
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# 0 - Default value
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# xpi0 configs
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# - flash driver: hpm_xpi
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# - flash ctrl index: 0xF3040000
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# - base address: 0x80000000
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# - flash size: 0x1000000
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flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
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proc init_clock {} {
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mww 0xF4000800 0xFFFFFFFF
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mww 0xF4000810 0xFFFFFFFF
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mww 0xF4000820 0xFFFFFFFF
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mww 0xF4000830 0xFFFFFFFF
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echo "clocks has been enabled!"
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}
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proc init_sdram { } {
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# configure femc frequency
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# 166Mhz pll0_clk1: 333Mhz divide by 2
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mww 0xF4001808 0x201
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# PA25
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mww 0xF40400C8 0xC
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# PA26
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mww 0xF40400D0 0xC
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# PA27
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mww 0xF40400D8 0xC
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# PA28
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mww 0xF40400E0 0xC
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# PA29
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mww 0xF40400E8 0xC
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# PA30
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mww 0xF40400F0 0xC
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# PA31
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mww 0xF40400F8 0xC
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# PB00
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mww 0xF4040100 0xC
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# PB01
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mww 0xF4040108 0xC
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# PB02
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mww 0xF4040110 0xC
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# PB03
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mww 0xF4040118 0xC
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# PB04
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mww 0xF4040120 0xC
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# PB05
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mww 0xF4040128 0xC
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# PB06
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mww 0xF4040130 0xC
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# PB07
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mww 0xF4040138 0xC
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# PB08
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mww 0xF4040140 0xC
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# PB09
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mww 0xF4040148 0xC
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# PB10
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mww 0xF4040150 0xC
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# PB11
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mww 0xF4040158 0xC
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# PB12
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mww 0xF4040160 0xC
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# PB13
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mww 0xF4040168 0xC
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# PB14
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mww 0xF4040170 0xC
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# PB15
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mww 0xF4040178 0xC
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# PB16
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mww 0xF4040180 0xC
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# PB17
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mww 0xF4040188 0xC
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# PB18
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mww 0xF4040190 0xC
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# PB19
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mww 0xF4040198 0xC
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# PB20
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mww 0xF40401A0 0xC
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# PB21
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mww 0xF40401A8 0xC
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# PB22
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mww 0xF40401B0 0xC
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# PB23
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mww 0xF40401B8 0xC
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# PB24
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mww 0xF40401C0 0xC
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# PB25
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mww 0xF40401C8 0xC
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# PB26
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mww 0xF40401D0 0xC
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# PB27
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mww 0xF40401D8 0xC
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# PB28
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mww 0xF40401E0 0xC
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# PB29
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mww 0xF40401E8 0xC
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# PB30
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mww 0xF40401F0 0xC
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# PB31
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mww 0xF40401F8 0xC
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# femc configuration
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mww 0xF3050000 0x1
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sleep 10
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mww 0xF3050000 0x2
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mww 0xF3050008 0x30524
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mww 0xF305000C 0x6030524
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mww 0xF3050000 0x10000004
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# 32MB
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mww 0xF3050010 0x4000001b
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mww 0xF3050014 0
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# 16-bit
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mww 0xF3050040 0xf31
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# 166Mhz configuration
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mww 0xF3050044 0x884e33
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mww 0xF3050048 0x1020d0d
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mww 0xF3050048 0x1020d0d
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mww 0xF305004C 0x2020300
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# config delay cell
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mww 0xF3050150 0x2000
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mww 0xF3050094 0
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mww 0xF3050098 0
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# precharge all
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mww 0xF3050090 0x40000000
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mww 0xF305009C 0xA55A000F
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sleep 500
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mww 0xF305003C 0x3
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# auto refresh
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mww 0xF305009C 0xA55A000C
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sleep 500
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mww 0xF305003C 0x3
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mww 0xF305009C 0xA55A000C
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sleep 500
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mww 0xF305003C 0x3
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# set mode
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mww 0xF30500A0 0x33
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mww 0xF305009C 0xA55A000A
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sleep 500
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mww 0xF305003C 0x3
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mww 0xF305004C 0x2020301
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echo "SDRAM has been initialized"
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}
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$_TARGET0 configure -event reset-init {
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init_clock
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init_sdram
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}
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