target/arm: opcodes: rename CamelCase symbols and uppercase variables
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6340 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
This commit is contained in:
Antonio Borneo
@@ -36,184 +36,184 @@
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/* ARM mode instructions */
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/* Store multiple increment after
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* Rn: base register
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* List: for each bit in list: store register
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* S: in privileged mode: store user-mode registers
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* W = 1: update the base register. W = 0: leave the base register untouched
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* rn: base register
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* list: for each bit in list: store register
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* s: in privileged mode: store user-mode registers
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* w = 1: update the base register. w = 0: leave the base register untouched
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*/
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#define ARMV4_5_STMIA(Rn, List, S, W) \
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(0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
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#define ARMV4_5_STMIA(rn, list, s, w) \
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(0xe8800000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
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/* Load multiple increment after
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* Rn: base register
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* List: for each bit in list: store register
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* S: in privileged mode: store user-mode registers
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* W = 1: update the base register. W = 0: leave the base register untouched
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* rn: base register
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* list: for each bit in list: store register
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* s: in privileged mode: store user-mode registers
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* w = 1: update the base register. w = 0: leave the base register untouched
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*/
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#define ARMV4_5_LDMIA(Rn, List, S, W) \
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(0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
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#define ARMV4_5_LDMIA(rn, list, s, w) \
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(0xe8900000 | ((s) << 22) | ((w) << 21) | ((rn) << 16) | (list))
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/* MOV r8, r8 */
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#define ARMV4_5_NOP (0xe1a08008)
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/* Move PSR to general purpose register
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* R = 1: SPSR R = 0: CPSR
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* Rn: target register
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* r = 1: SPSR r = 0: CPSR
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* rn: target register
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*/
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#define ARMV4_5_MRS(Rn, R) (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
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#define ARMV4_5_MRS(rn, r) (0xe10f0000 | ((r) << 22) | ((rn) << 12))
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/* Store register
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* Rd: register to store
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* Rn: base register
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_STR(rd, rn) (0xe5800000 | ((rd) << 12) | ((rn) << 16))
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/* Load register
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* Rd: register to load
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* Rn: base register
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_LDR(rd, rn) (0xe5900000 | ((rd) << 12) | ((rn) << 16))
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/* Move general purpose register to PSR
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* R = 1: SPSR R = 0: CPSR
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* Field: Field mask
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* r = 1: SPSR r = 0: CPSR
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* field: Field mask
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* 1: control field 2: extension field 4: status field 8: flags field
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* Rm: source register
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* rm: source register
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*/
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#define ARMV4_5_MSR_GP(Rm, Field, R) \
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(0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
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#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) \
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(0xe320f000 | (Im) | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
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#define ARMV4_5_MSR_GP(rm, field, r) \
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(0xe120f000 | (rm) | ((field) << 16) | ((r) << 22))
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#define ARMV4_5_MSR_IM(im, rotate, field, r) \
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(0xe320f000 | (im) | ((rotate) << 8) | ((field) << 16) | ((r) << 22))
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/* Load Register Word Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDRW_IP(Rd, Rn) (0xe4900004 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_LDRW_IP(rd, rn) (0xe4900004 | ((rd) << 12) | ((rn) << 16))
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/* Load Register Halfword Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_LDRH_IP(rd, rn) (0xe0d000b2 | ((rd) << 12) | ((rn) << 16))
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/* Load Register Byte Immediate Post-Index
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* Rd: register to load
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* Rn: base register
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* rd: register to load
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* rn: base register
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*/
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#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_LDRB_IP(rd, rn) (0xe4d00001 | ((rd) << 12) | ((rn) << 16))
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/* Store register Word Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STRW_IP(Rd, Rn) (0xe4800004 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_STRW_IP(rd, rn) (0xe4800004 | ((rd) << 12) | ((rn) << 16))
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/* Store register Halfword Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_STRH_IP(rd, rn) (0xe0c000b2 | ((rd) << 12) | ((rn) << 16))
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/* Store register Byte Immediate Post-Index
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* Rd: register to store
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* Rn: base register
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* rd: register to store
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* rn: base register
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*/
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#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
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#define ARMV4_5_STRB_IP(rd, rn) (0xe4c00001 | ((rd) << 12) | ((rn) << 16))
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/* Branch (and Link)
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* Im: Branch target (left-shifted by 2 bits, added to PC)
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* L: 1: branch and link 0: branch only
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* im: Branch target (left-shifted by 2 bits, added to PC)
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* l: 1: branch and link 0: branch only
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*/
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#define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
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#define ARMV4_5_B(im, l) (0xea000000 | (im) | ((l) << 24))
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/* Branch and exchange (ARM state)
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* Rm: register holding branch target address
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* rm: register holding branch target address
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*/
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#define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
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#define ARMV4_5_BX(rm) (0xe12fff10 | (rm))
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/* Copies two words from two ARM core registers
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* into a doubleword extension register, or
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* from a doubleword extension register to two ARM core registers.
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* See Armv7-A arch reference manual section A8.8.345
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* Rt: Arm core register 1
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* Rt2: Arm core register 2
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* Vm: The doubleword extension register
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* M: m = UInt(M:Vm);
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* rt: Arm core register 1
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* rt2: Arm core register 2
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* vm: The doubleword extension register
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* m: m = UInt(m:vm);
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* op: to_arm_registers = (op == ‘1’);
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*/
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#define ARMV4_5_VMOV(op, Rt2, Rt, M, Vm) \
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(0xec400b10 | ((op) << 20) | ((Rt2) << 16) | \
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((Rt) << 12) | ((M) << 5) | (Vm))
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#define ARMV4_5_VMOV(op, rt2, rt, m, vm) \
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(0xec400b10 | ((op) << 20) | ((rt2) << 16) | \
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((rt) << 12) | ((m) << 5) | (vm))
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/* Moves the value of the FPSCR to an ARM core register
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* Rt: Arm core register
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* rt: Arm core register
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*/
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#define ARMV4_5_VMRS(Rt) (0xeef10a10 | ((Rt) << 12))
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#define ARMV4_5_VMRS(rt) (0xeef10a10 | ((rt) << 12))
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/* Moves the value of an ARM core register to the FPSCR.
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* Rt: Arm core register
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* rt: Arm core register
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*/
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#define ARMV4_5_VMSR(Rt) (0xeee10a10 | ((Rt) << 12))
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#define ARMV4_5_VMSR(rt) (0xeee10a10 | ((rt) << 12))
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/* Store data from coprocessor to consecutive memory
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* See Armv7-A arch doc section A8.6.187
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* P: 1=index mode (offset from Rn)
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* U: 1=add, 0=subtract Rn address with imm
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* D: Opcode D encoding
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* W: write back the offset start address to the Rn register
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* CP: Coprocessor number (4 bits)
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* CRd: Coprocessor source register (4 bits)
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* Rn: Base register for memory address (4 bits)
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* p: 1=index mode (offset from rn)
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* u: 1=add, 0=subtract rn address with imm
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* d: Opcode D encoding
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* w: write back the offset start address to the rn register
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* cp: Coprocessor number (4 bits)
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* crd: Coprocessor source register (4 bits)
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* rn: Base register for memory address (4 bits)
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* imm: Immediate value (0 - 1020, must be divisible by 4)
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*/
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#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \
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(0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
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((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2))
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#define ARMV4_5_STC(p, u, d, w, cp, crd, rn, imm) \
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(0xec000000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
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((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm)>>2))
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/* Loads data from consecutive memory to coprocessor
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* See Armv7-A arch doc section A8.6.51
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* P: 1=index mode (offset from Rn)
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* U: 1=add, 0=subtract Rn address with imm
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* D: Opcode D encoding
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* W: write back the offset start address to the Rn register
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* CP: Coprocessor number (4 bits)
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* CRd: Coprocessor dest register (4 bits)
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* Rn: Base register for memory address (4 bits)
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* p: 1=index mode (offset from rn)
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* u: 1=add, 0=subtract rn address with imm
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* d: Opcode D encoding
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* w: write back the offset start address to the rn register
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* cp: Coprocessor number (4 bits)
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* crd: Coprocessor dest register (4 bits)
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* rn: Base register for memory address (4 bits)
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* imm: Immediate value (0 - 1020, must be divisible by 4)
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*/
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#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \
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(0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \
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((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2))
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#define ARMV4_5_LDC(p, u, d, w, cp, crd, rn, imm) \
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(0xec100000 | ((p) << 24) | ((u) << 23) | ((d) << 22) | \
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((w) << 21) | ((rn) << 16) | ((crd) << 12) | ((cp) << 8) | ((imm) >> 2))
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/* Move to ARM register from coprocessor
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* CP: Coprocessor number
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* cp: Coprocessor number
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* op1: Coprocessor opcode
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* Rd: destination register
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* CRn: first coprocessor operand
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* CRm: second coprocessor operand
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* rd: destination register
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* crn: first coprocessor operand
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* crm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) \
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(0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
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| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
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#define ARMV4_5_MRC(cp, op1, rd, crn, crm, op2) \
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(0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
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| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
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/* Move to coprocessor from ARM register
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* CP: Coprocessor number
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* cp: Coprocessor number
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* op1: Coprocessor opcode
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* Rd: destination register
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* CRn: first coprocessor operand
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* CRm: second coprocessor operand
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* rd: destination register
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* crn: first coprocessor operand
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* crm: second coprocessor operand
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* op2: Second coprocessor opcode
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*/
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#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) \
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(0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) \
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| ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
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#define ARMV4_5_MCR(cp, op1, rd, crn, crm, op2) \
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(0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
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| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
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/* Breakpoint instruction (ARMv5)
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* Im: 16-bit immediate
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* im: 16-bit immediate
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*/
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#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 4) | (Im & 0xf))
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#define ARMV5_BKPT(im) (0xe1200070 | ((im & 0xfff0) << 4) | (im & 0xf))
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/* Thumb mode instructions
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@@ -228,45 +228,45 @@
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*/
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/* Store register (Thumb mode)
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* Rd: source register
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* Rn: base register
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* rd: source register
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* rn: base register
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*/
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#define ARMV4_5_T_STR(Rd, Rn) \
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((0x6000 | (Rd) | ((Rn) << 3)) | \
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((0x6000 | (Rd) | ((Rn) << 3)) << 16))
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#define ARMV4_5_T_STR(rd, rn) \
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((0x6000 | (rd) | ((rn) << 3)) | \
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((0x6000 | (rd) | ((rn) << 3)) << 16))
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/* Load register (Thumb state)
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* Rd: destination register
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* Rn: base register
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* rd: destination register
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* rn: base register
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*/
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#define ARMV4_5_T_LDR(Rd, Rn) \
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((0x6800 | ((Rn) << 3) | (Rd)) \
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| ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
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#define ARMV4_5_T_LDR(rd, rn) \
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((0x6800 | ((rn) << 3) | (rd)) \
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| ((0x6800 | ((rn) << 3) | (rd)) << 16))
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/* Load multiple (Thumb state)
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* Rn: base register
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* List: for each bit in list: store register
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* rn: base register
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* list: for each bit in list: store register
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*/
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#define ARMV4_5_T_LDMIA(Rn, List) \
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((0xc800 | ((Rn) << 8) | (List)) \
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| ((0xc800 | ((Rn) << 8) | (List)) << 16))
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#define ARMV4_5_T_LDMIA(rn, list) \
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((0xc800 | ((rn) << 8) | (list)) \
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| ((0xc800 | ((rn) << 8) | (list)) << 16))
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/* Load register with PC relative addressing
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* Rd: register to load
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* rd: register to load
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*/
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#define ARMV4_5_T_LDR_PCREL(Rd) \
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((0x4800 | ((Rd) << 8)) \
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| ((0x4800 | ((Rd) << 8)) << 16))
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#define ARMV4_5_T_LDR_PCREL(rd) \
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((0x4800 | ((rd) << 8)) \
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| ((0x4800 | ((rd) << 8)) << 16))
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/* Move hi register (Thumb mode)
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* Rd: destination register
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* Rm: source register
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* rd: destination register
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* rm: source register
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*/
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#define ARMV4_5_T_MOV(Rd, Rm) \
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((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
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(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) \
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| ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | \
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(((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
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#define ARMV4_5_T_MOV(rd, rm) \
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((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
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(((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) \
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| ((0x4600 | ((rd) & 0x7) | (((rd) & 0x8) << 4) | \
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(((rm) & 0x7) << 3) | (((rm) & 0x8) << 3)) << 16))
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/* No operation (Thumb mode)
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* NOTE: this is "MOV r8, r8" ... Thumb2 adds two
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@@ -275,63 +275,63 @@
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#define ARMV4_5_T_NOP (0x46c0 | (0x46c0 << 16))
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/* Move immediate to register (Thumb state)
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* Rd: destination register
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* Im: 8-bit immediate value
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* rd: destination register
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* im: 8-bit immediate value
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*/
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#define ARMV4_5_T_MOV_IM(Rd, Im) \
|
||||
((0x2000 | ((Rd) << 8) | (Im)) \
|
||||
| ((0x2000 | ((Rd) << 8) | (Im)) << 16))
|
||||
#define ARMV4_5_T_MOV_IM(rd, im) \
|
||||
((0x2000 | ((rd) << 8) | (im)) \
|
||||
| ((0x2000 | ((rd) << 8) | (im)) << 16))
|
||||
|
||||
/* Branch and Exchange
|
||||
* Rm: register containing branch target
|
||||
* rm: register containing branch target
|
||||
*/
|
||||
#define ARMV4_5_T_BX(Rm) \
|
||||
((0x4700 | ((Rm) << 3)) \
|
||||
| ((0x4700 | ((Rm) << 3)) << 16))
|
||||
#define ARMV4_5_T_BX(rm) \
|
||||
((0x4700 | ((rm) << 3)) \
|
||||
| ((0x4700 | ((rm) << 3)) << 16))
|
||||
|
||||
/* Branch (Thumb state)
|
||||
* Imm: Branch target
|
||||
* imm: Branch target
|
||||
*/
|
||||
#define ARMV4_5_T_B(Imm) \
|
||||
((0xe000 | (Imm)) \
|
||||
| ((0xe000 | (Imm)) << 16))
|
||||
#define ARMV4_5_T_B(imm) \
|
||||
((0xe000 | (imm)) \
|
||||
| ((0xe000 | (imm)) << 16))
|
||||
|
||||
/* Breakpoint instruction (ARMv5) (Thumb state)
|
||||
* Im: 8-bit immediate
|
||||
*/
|
||||
#define ARMV5_T_BKPT(Im) \
|
||||
((0xbe00 | (Im)) \
|
||||
| ((0xbe00 | (Im)) << 16))
|
||||
#define ARMV5_T_BKPT(im) \
|
||||
((0xbe00 | (im)) \
|
||||
| ((0xbe00 | (im)) << 16))
|
||||
|
||||
/* Move to Register from Special Register
|
||||
* 32 bit Thumb2 instruction
|
||||
* Rd: destination register
|
||||
* SYSm: source special register
|
||||
* rd: destination register
|
||||
* sysm: source special register
|
||||
*/
|
||||
#define ARM_T2_MRS(Rd, SYSm) \
|
||||
((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
|
||||
#define ARM_T2_MRS(rd, sysm) \
|
||||
((0xF3EF) | ((0x8000 | (rd << 8) | sysm) << 16))
|
||||
|
||||
/* Move from Register from Special Register
|
||||
* 32 bit Thumb2 instruction
|
||||
* Rd: source register
|
||||
* SYSm: destination special register
|
||||
* rd: source register
|
||||
* sysm: destination special register
|
||||
*/
|
||||
#define ARM_T2_MSR(SYSm, Rn) \
|
||||
((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
|
||||
#define ARM_T2_MSR(sysm, rn) \
|
||||
((0xF380 | (rn << 8)) | ((0x8800 | sysm) << 16))
|
||||
|
||||
/* Change Processor State.
|
||||
* 16 bit Thumb2 instruction
|
||||
* Rd: source register
|
||||
* rd: source register
|
||||
* IF: A_FLAG and/or I_FLAG and/or F_FLAG
|
||||
*/
|
||||
#define A_FLAG 4
|
||||
#define I_FLAG 2
|
||||
#define F_FLAG 1
|
||||
#define ARM_T2_CPSID(IF) \
|
||||
((0xB660 | (1 << 8) | ((IF)&0x3)) \
|
||||
| ((0xB660 | (1 << 8) | ((IF)&0x3)) << 16))
|
||||
#define ARM_T2_CPSIE(IF) \
|
||||
((0xB660 | (0 << 8) | ((IF)&0x3)) \
|
||||
| ((0xB660 | (0 << 8) | ((IF)&0x3)) << 16))
|
||||
#define ARM_T2_CPSID(_if) \
|
||||
((0xB660 | (1 << 8) | ((_if)&0x3)) \
|
||||
| ((0xB660 | (1 << 8) | ((_if)&0x3)) << 16))
|
||||
#define ARM_T2_CPSIE(_if) \
|
||||
((0xB660 | (0 << 8) | ((_if)&0x3)) \
|
||||
| ((0xB660 | (0 << 8) | ((_if)&0x3)) << 16))
|
||||
|
||||
#endif /* OPENOCD_TARGET_ARM_OPCODES_H */
|
||||
|
||||
Reference in New Issue
Block a user