target/arm: opcodes: rename CamelCase symbols and uppercase variables
No major cross dependencies, mostly changes internal to each file/function. Change-Id: I1325560ef0350517d86d4927cb17ceaae81b75d2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/6340 Tested-by: jenkins Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Xiang W <wxjstz@126.com>
This commit is contained in:
Antonio Borneo
@@ -31,7 +31,7 @@
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#include "register.h"
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#include <helper/log.h>
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static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
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static uint32_t arm_shift(uint8_t shift, uint32_t rm,
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uint32_t shift_amount, uint8_t *carry)
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{
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uint32_t return_value = 0;
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@@ -39,22 +39,22 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
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if (shift == 0x0) { /* LSL */
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if ((shift_amount > 0) && (shift_amount <= 32)) {
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return_value = Rm << shift_amount;
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*carry = Rm >> (32 - shift_amount);
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return_value = rm << shift_amount;
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*carry = rm >> (32 - shift_amount);
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} else if (shift_amount > 32) {
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return_value = 0x0;
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*carry = 0x0;
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} else /* (shift_amount == 0) */
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return_value = Rm;
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return_value = rm;
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} else if (shift == 0x1) { /* LSR */
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if ((shift_amount > 0) && (shift_amount <= 32)) {
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return_value = Rm >> shift_amount;
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*carry = (Rm >> (shift_amount - 1)) & 1;
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return_value = rm >> shift_amount;
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*carry = (rm >> (shift_amount - 1)) & 1;
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} else if (shift_amount > 32) {
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return_value = 0x0;
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*carry = 0x0;
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} else /* (shift_amount == 0) */
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return_value = Rm;
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return_value = rm;
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} else if (shift == 0x2) { /* ASR */
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if ((shift_amount > 0) && (shift_amount <= 32)) {
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/* C right shifts of unsigned values are guaranteed to
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@@ -62,11 +62,11 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
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* shift (shift in signed-bit) by adding the sign bit
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* manually
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*/
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return_value = Rm >> shift_amount;
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if (Rm & 0x80000000)
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return_value = rm >> shift_amount;
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if (rm & 0x80000000)
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return_value |= 0xffffffff << (32 - shift_amount);
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} else if (shift_amount > 32) {
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if (Rm & 0x80000000) {
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if (rm & 0x80000000) {
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return_value = 0xffffffff;
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*carry = 0x1;
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} else {
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@@ -74,20 +74,20 @@ static uint32_t arm_shift(uint8_t shift, uint32_t Rm,
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*carry = 0x0;
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}
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} else /* (shift_amount == 0) */
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return_value = Rm;
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return_value = rm;
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} else if (shift == 0x3) { /* ROR */
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if (shift_amount == 0)
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return_value = Rm;
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return_value = rm;
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else {
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shift_amount = shift_amount % 32;
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return_value = (Rm >> shift_amount) | (Rm << (32 - shift_amount));
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return_value = (rm >> shift_amount) | (rm << (32 - shift_amount));
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*carry = (return_value >> 31) & 0x1;
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}
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} else if (shift == 0x4) { /* RRX */
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return_value = Rm >> 1;
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return_value = rm >> 1;
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if (*carry)
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Rm |= 0x80000000;
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*carry = Rm & 0x1;
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rm |= 0x80000000;
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*carry = rm & 0x1;
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}
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return return_value;
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@@ -111,25 +111,25 @@ static uint32_t arm_shifter_operand(struct arm_sim_interface *sim,
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if (variant == 0) /* 32-bit immediate */
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return_value = shifter_operand.immediate.immediate;
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else if (variant == 1) {/* immediate shift */
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uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm);
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uint32_t rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.rm);
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/* adjust RM in case the PC is being read */
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if (shifter_operand.immediate_shift.Rm == 15)
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Rm += 2 * instruction_size;
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if (shifter_operand.immediate_shift.rm == 15)
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rm += 2 * instruction_size;
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return_value = arm_shift(shifter_operand.immediate_shift.shift,
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Rm, shifter_operand.immediate_shift.shift_imm,
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rm, shifter_operand.immediate_shift.shift_imm,
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shifter_carry_out);
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} else if (variant == 2) { /* register shift */
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uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm);
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uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs);
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uint32_t rm = sim->get_reg_mode(sim, shifter_operand.register_shift.rm);
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uint32_t rs = sim->get_reg_mode(sim, shifter_operand.register_shift.rs);
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/* adjust RM in case the PC is being read */
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if (shifter_operand.register_shift.Rm == 15)
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Rm += 2 * instruction_size;
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if (shifter_operand.register_shift.rm == 15)
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rm += 2 * instruction_size;
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return_value = arm_shift(shifter_operand.immediate_shift.shift,
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Rm, Rs, shifter_carry_out);
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rm, rs, shifter_carry_out);
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} else {
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LOG_ERROR("BUG: shifter_operand.variant not 0, 1 or 2");
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return_value = 0xffffffff;
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@@ -324,8 +324,8 @@ static int arm_simulate_step_core(struct target *target,
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sim->set_reg(sim, 15, target_address);
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else if (instruction.type == ARM_BL) {
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uint32_t old_pc = sim->get_reg(sim, 15);
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int T = (sim->get_state(sim) == ARM_STATE_THUMB);
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sim->set_reg_mode(sim, 14, old_pc + 4 + T);
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int t = (sim->get_state(sim) == ARM_STATE_THUMB);
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sim->set_reg_mode(sim, 14, old_pc + 4 + t);
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sim->set_reg(sim, 15, target_address);
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} else if (instruction.type == ARM_BX) {
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if (target_address & 0x1)
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@@ -335,8 +335,8 @@ static int arm_simulate_step_core(struct target *target,
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sim->set_reg(sim, 15, target_address & 0xfffffffe);
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} else if (instruction.type == ARM_BLX) {
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uint32_t old_pc = sim->get_reg(sim, 15);
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int T = (sim->get_state(sim) == ARM_STATE_THUMB);
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sim->set_reg_mode(sim, 14, old_pc + 4 + T);
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int t = (sim->get_state(sim) == ARM_STATE_THUMB);
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sim->set_reg_mode(sim, 14, old_pc + 4 + t);
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if (target_address & 0x1)
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sim->set_state(sim, ARM_STATE_THUMB);
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@@ -351,16 +351,16 @@ static int arm_simulate_step_core(struct target *target,
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/* data processing instructions, except compare instructions (CMP, CMN, TST, TEQ) */
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else if (((instruction.type >= ARM_AND) && (instruction.type <= ARM_RSC))
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|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN))) {
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uint32_t Rd, Rn, shifter_operand;
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uint8_t C = sim->get_cpsr(sim, 29, 1);
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uint32_t rd, rn, shifter_operand;
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uint8_t c = sim->get_cpsr(sim, 29, 1);
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uint8_t carry_out;
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Rd = 0x0;
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rd = 0x0;
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/* ARM_MOV and ARM_MVN does not use Rn */
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if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
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Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn);
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rn = sim->get_reg_mode(sim, instruction.info.data_proc.rn);
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else
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Rn = 0;
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rn = 0;
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shifter_operand = arm_shifter_operand(sim,
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instruction.info.data_proc.variant,
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@@ -368,53 +368,53 @@ static int arm_simulate_step_core(struct target *target,
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&carry_out);
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/* adjust Rn in case the PC is being read */
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if (instruction.info.data_proc.Rn == 15)
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Rn += 2 * instruction_size;
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if (instruction.info.data_proc.rn == 15)
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rn += 2 * instruction_size;
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if (instruction.type == ARM_AND)
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Rd = Rn & shifter_operand;
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rd = rn & shifter_operand;
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else if (instruction.type == ARM_EOR)
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Rd = Rn ^ shifter_operand;
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rd = rn ^ shifter_operand;
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else if (instruction.type == ARM_SUB)
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Rd = Rn - shifter_operand;
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rd = rn - shifter_operand;
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else if (instruction.type == ARM_RSB)
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Rd = shifter_operand - Rn;
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rd = shifter_operand - rn;
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else if (instruction.type == ARM_ADD)
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Rd = Rn + shifter_operand;
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rd = rn + shifter_operand;
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else if (instruction.type == ARM_ADC)
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Rd = Rn + shifter_operand + (C & 1);
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rd = rn + shifter_operand + (c & 1);
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else if (instruction.type == ARM_SBC)
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Rd = Rn - shifter_operand - (C & 1) ? 0 : 1;
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rd = rn - shifter_operand - (c & 1) ? 0 : 1;
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else if (instruction.type == ARM_RSC)
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Rd = shifter_operand - Rn - (C & 1) ? 0 : 1;
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rd = shifter_operand - rn - (c & 1) ? 0 : 1;
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else if (instruction.type == ARM_ORR)
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Rd = Rn | shifter_operand;
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rd = rn | shifter_operand;
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else if (instruction.type == ARM_BIC)
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Rd = Rn & ~(shifter_operand);
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rd = rn & ~(shifter_operand);
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else if (instruction.type == ARM_MOV)
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Rd = shifter_operand;
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rd = shifter_operand;
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else if (instruction.type == ARM_MVN)
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Rd = ~shifter_operand;
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rd = ~shifter_operand;
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else
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LOG_WARNING("unhandled instruction type");
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if (dry_run_pc) {
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if (instruction.info.data_proc.Rd == 15)
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*dry_run_pc = Rd & ~1;
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if (instruction.info.data_proc.rd == 15)
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*dry_run_pc = rd & ~1;
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else
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*dry_run_pc = current_pc + instruction_size;
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return ERROR_OK;
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} else {
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if (instruction.info.data_proc.Rd == 15) {
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sim->set_reg_mode(sim, 15, Rd & ~1);
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if (Rd & 1)
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if (instruction.info.data_proc.rd == 15) {
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sim->set_reg_mode(sim, 15, rd & ~1);
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if (rd & 1)
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sim->set_state(sim, ARM_STATE_THUMB);
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else
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sim->set_state(sim, ARM_STATE_ARM);
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return ERROR_OK;
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}
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sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
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sim->set_reg_mode(sim, instruction.info.data_proc.rd, rd);
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LOG_WARNING("no updating of flags yet");
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}
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}
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@@ -429,31 +429,31 @@ static int arm_simulate_step_core(struct target *target,
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/* load register instructions */
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else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH)) {
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uint32_t load_address = 0, modified_address = 0, load_value = 0;
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uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
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uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store.rn);
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/* adjust Rn in case the PC is being read */
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if (instruction.info.load_store.Rn == 15)
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Rn += 2 * instruction_size;
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if (instruction.info.load_store.rn == 15)
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rn += 2 * instruction_size;
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if (instruction.info.load_store.offset_mode == 0) {
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if (instruction.info.load_store.U)
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modified_address = Rn + instruction.info.load_store.offset.offset;
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if (instruction.info.load_store.u)
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modified_address = rn + instruction.info.load_store.offset.offset;
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else
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modified_address = Rn - instruction.info.load_store.offset.offset;
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modified_address = rn - instruction.info.load_store.offset.offset;
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} else if (instruction.info.load_store.offset_mode == 1) {
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uint32_t offset;
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uint32_t Rm = sim->get_reg_mode(sim,
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instruction.info.load_store.offset.reg.Rm);
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uint32_t rm = sim->get_reg_mode(sim,
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instruction.info.load_store.offset.reg.rm);
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uint8_t shift = instruction.info.load_store.offset.reg.shift;
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uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
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uint8_t carry = sim->get_cpsr(sim, 29, 1);
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offset = arm_shift(shift, Rm, shift_imm, &carry);
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offset = arm_shift(shift, rm, shift_imm, &carry);
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if (instruction.info.load_store.U)
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modified_address = Rn + offset;
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if (instruction.info.load_store.u)
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modified_address = rn + offset;
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else
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modified_address = Rn - offset;
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modified_address = rn - offset;
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} else
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LOG_ERROR("BUG: offset_mode neither 0 (offset) nor 1 (scaled register)");
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@@ -463,7 +463,7 @@ static int arm_simulate_step_core(struct target *target,
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* the base address register
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*/
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load_address = modified_address;
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modified_address = Rn;
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modified_address = rn;
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} else if (instruction.info.load_store.index_mode == 1) {
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/* pre-indexed mode
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* we load from the modified address, and write it
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@@ -475,17 +475,17 @@ static int arm_simulate_step_core(struct target *target,
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* we load from the unmodified address, and write the
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* modified address back
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*/
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load_address = Rn;
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load_address = rn;
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}
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if ((!dry_run_pc) || (instruction.info.load_store.Rd == 15)) {
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if ((!dry_run_pc) || (instruction.info.load_store.rd == 15)) {
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retval = target_read_u32(target, load_address, &load_value);
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if (retval != ERROR_OK)
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return retval;
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}
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if (dry_run_pc) {
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if (instruction.info.load_store.Rd == 15)
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if (instruction.info.load_store.rd == 15)
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*dry_run_pc = load_value & ~1;
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else
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*dry_run_pc = current_pc + instruction_size;
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@@ -494,10 +494,10 @@ static int arm_simulate_step_core(struct target *target,
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if ((instruction.info.load_store.index_mode == 1) ||
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(instruction.info.load_store.index_mode == 2))
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sim->set_reg_mode(sim,
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instruction.info.load_store.Rn,
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instruction.info.load_store.rn,
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modified_address);
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if (instruction.info.load_store.Rd == 15) {
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if (instruction.info.load_store.rd == 15) {
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sim->set_reg_mode(sim, 15, load_value & ~1);
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if (load_value & 1)
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sim->set_state(sim, ARM_STATE_THUMB);
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@@ -505,13 +505,13 @@ static int arm_simulate_step_core(struct target *target,
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sim->set_state(sim, ARM_STATE_ARM);
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return ERROR_OK;
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}
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sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
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sim->set_reg_mode(sim, instruction.info.load_store.rd, load_value);
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}
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}
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/* load multiple instruction */
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else if (instruction.type == ARM_LDM) {
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int i;
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uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
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uint32_t rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.rn);
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uint32_t load_values[16];
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int bits_set = 0;
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@@ -522,24 +522,24 @@ static int arm_simulate_step_core(struct target *target,
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switch (instruction.info.load_store_multiple.addressing_mode) {
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case 0: /* Increment after */
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/* Rn = Rn; */
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/* rn = rn; */
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break;
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case 1: /* Increment before */
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Rn = Rn + 4;
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rn = rn + 4;
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break;
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case 2: /* Decrement after */
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Rn = Rn - (bits_set * 4) + 4;
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rn = rn - (bits_set * 4) + 4;
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break;
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case 3: /* Decrement before */
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Rn = Rn - (bits_set * 4);
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rn = rn - (bits_set * 4);
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break;
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}
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for (i = 0; i < 16; i++) {
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if (instruction.info.load_store_multiple.register_list & (1 << i)) {
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if ((!dry_run_pc) || (i == 15))
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target_read_u32(target, Rn, &load_values[i]);
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Rn += 4;
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target_read_u32(target, rn, &load_values[i]);
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rn += 4;
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}
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}
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@@ -551,7 +551,7 @@ static int arm_simulate_step_core(struct target *target,
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} else {
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int update_cpsr = 0;
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if (instruction.info.load_store_multiple.S) {
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if (instruction.info.load_store_multiple.s) {
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if (instruction.info.load_store_multiple.register_list & 0x8000)
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update_cpsr = 1;
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}
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@@ -576,8 +576,8 @@ static int arm_simulate_step_core(struct target *target,
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}
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/* base register writeback */
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if (instruction.info.load_store_multiple.W)
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sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
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if (instruction.info.load_store_multiple.w)
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sim->set_reg_mode(sim, instruction.info.load_store_multiple.rn, rn);
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if (instruction.info.load_store_multiple.register_list & 0x8000)
|
||||
@@ -591,8 +591,8 @@ static int arm_simulate_step_core(struct target *target,
|
||||
if (dry_run_pc) {
|
||||
/* STM wont affect PC (advance by instruction size */
|
||||
} else {
|
||||
uint32_t Rn = sim->get_reg_mode(sim,
|
||||
instruction.info.load_store_multiple.Rn);
|
||||
uint32_t rn = sim->get_reg_mode(sim,
|
||||
instruction.info.load_store_multiple.rn);
|
||||
int bits_set = 0;
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
@@ -602,30 +602,30 @@ static int arm_simulate_step_core(struct target *target,
|
||||
|
||||
switch (instruction.info.load_store_multiple.addressing_mode) {
|
||||
case 0: /* Increment after */
|
||||
/* Rn = Rn; */
|
||||
/* rn = rn; */
|
||||
break;
|
||||
case 1: /* Increment before */
|
||||
Rn = Rn + 4;
|
||||
rn = rn + 4;
|
||||
break;
|
||||
case 2: /* Decrement after */
|
||||
Rn = Rn - (bits_set * 4) + 4;
|
||||
rn = rn - (bits_set * 4) + 4;
|
||||
break;
|
||||
case 3: /* Decrement before */
|
||||
Rn = Rn - (bits_set * 4);
|
||||
rn = rn - (bits_set * 4);
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
||||
if (instruction.info.load_store_multiple.register_list & (1 << i)) {
|
||||
target_write_u32(target, Rn, sim->get_reg_mode(sim, i));
|
||||
Rn += 4;
|
||||
target_write_u32(target, rn, sim->get_reg_mode(sim, i));
|
||||
rn += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* base register writeback */
|
||||
if (instruction.info.load_store_multiple.W)
|
||||
if (instruction.info.load_store_multiple.w)
|
||||
sim->set_reg_mode(sim,
|
||||
instruction.info.load_store_multiple.Rn, Rn);
|
||||
instruction.info.load_store_multiple.rn, rn);
|
||||
|
||||
}
|
||||
} else if (!dry_run_pc) {
|
||||
|
||||
Reference in New Issue
Block a user