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quark_x10xx: add new target quark_x10xx

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Intel Quark X10xx SoC debug support added
Lakemont version 1 (LMT1) is the x86 core in Quark X10xx SoC
Generic x86 32-bit code is in x86_32_common.c/h

Change-Id: If2bf77275cd0277a82558cd9895b4c66155cf368
Signed-off-by: adrian.burns@intel.com
Reviewed-on: http://openocd.zylin.com/1829
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Adrian Burns
2014-02-06 17:11:15 +00:00
committed by Andreas Fritiofson
parent 005d85d56c
commit 1338cf60b9
11 changed files with 3193 additions and 5 deletions
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47
doc/openocd.texi
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@@ -156,9 +156,9 @@ USB-based, parallel port-based, and other standalone boxes that run
OpenOCD internally. @xref{Debug Adapter Hardware}.
@b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x) and
Cortex-M3 (Stellaris LM3, ST STM32 and Energy Micro EFM32) based cores to be
debugged via the GDB protocol.
ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
(Stellaris LM3, ST STM32 and Energy Micro EFM32) and Intel Quark (x10xx)
based cores to be debugged via the GDB protocol.
@b{Flash Programming:} Flash writing is supported for external
CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
@@ -7542,6 +7542,47 @@ the peripherals.
@xref{targetevents,,Target Events}.
@end deffn
@section Intel Architecture
Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32
(Pentium x86 ISA) compatible SoC. The core CPU in the X10xx is codenamed Lakemont.
Lakemont version 1 (LMT1) is used in X10xx. The CPU TAP (Lakemont TAP) is used for
software debug and the CLTAP is used for SoC level operations.
Useful docs are here: https://communities.intel.com/community/makers/documentation
@itemize
@item Intel Quark SoC X1000 OpenOCD/GDB/Eclipse App Note (web search for doc num 330015)
@item Intel Quark SoC X1000 Debug Operations User Guide (web search for doc num 329866)
@item Intel Quark SoC X1000 Datasheet (web search for doc num 329676)
@end itemize
@subsection x86 32-bit specific commands
The three main address spaces for x86 are memory, I/O and configuration space.
These commands allow a user to read and write to the 64Kbyte I/O address space.
@deffn Command {x86_32 idw} address
Display the contents of a 32-bit I/O port from address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 idh} address
Display the contents of a 16-bit I/O port from address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 idb} address
Display the contents of a 8-bit I/O port from address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 iww} address
Write the contents of a 32-bit I/O port to address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 iwh} address
Write the contents of a 16-bit I/O port to address range 0x0000 - 0xffff.
@end deffn
@deffn Command {x86_32 iwb} address
Write the contents of a 8-bit I/O port to address range 0x0000 - 0xffff.
@end deffn
@section OpenRISC Architecture
The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be