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armv7m_trace_itm_config: wait for ITMBusy to be cleared

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pg315 of CoreSight Components:

It is recommended that the ITMEn bit is cleared and waits for the
ITMBusy bit to be cleared, before changing any fields in the
Control Register, otherwise the behavior can be unpredictable.

Change-Id: Ie9a2b842825c98ee5edc9a35776320c668047769
Signed-off-by: Adrian Negreanu <adrian.negreanu@nxp.com>
Reviewed-on: http://openocd.zylin.com/6043
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Adrian Negreanu
2020-11-20 18:53:51 +02:00
committed by Antonio Borneo
parent fa76e036b9
commit 169e5bf186
2 changed files with 30 additions and 0 deletions
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28
src/target/armv7m_trace.c
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@@ -24,6 +24,7 @@
#include <target/cortex_m.h>
#include <target/armv7m_trace.h>
#include <jtag/interface.h>
#include <helper/time_support.h>
#define TRACE_BUF_SIZE 4096
@@ -162,6 +163,33 @@ int armv7m_trace_itm_config(struct target *target)
if (retval != ERROR_OK)
return retval;
/* pg315 of CoreSight Components
* It is recommended that the ITMEn bit is cleared and waits for the
* ITMBusy bit to be cleared, before changing any fields in the
* Control Register, otherwise the behavior can be unpredictable.
*/
uint32_t itm_tcr;
retval = target_read_u32(target, ITM_TCR, &itm_tcr);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target,
ITM_TCR,
itm_tcr & ~ITM_TCR_ITMENA_BIT
);
if (retval != ERROR_OK)
return retval;
int64_t then = timeval_ms() + 1000;
do {
retval = target_read_u32(target, ITM_TCR, &itm_tcr);
if (retval != ERROR_OK)
return retval;
if (timeval_ms() > then) {
LOG_ERROR("timeout waiting for ITM_TCR_BUSY_BIT");
return ERROR_FAIL;
}
} while (itm_tcr & ITM_TCR_BUSY_BIT);
/* Enable ITM, TXENA, set TraceBusID and other parameters */
retval = target_write_u32(target, ITM_TCR, (1 << 0) | (1 << 3) |
(trace_config->itm_diff_timestamps << 1) |