target/mips32: rework mips core register related functions
Update mips core definitions. Reworked mips core register structure and read/write function. Add coprocessor0 register definitions for target configuration. Change-Id: I59c1f4cc4020db8a78e8d79f7421b87382fa1709 Signed-off-by: Walter Ji <walter.ji@oss.cipunited.com> Reviewed-on: https://review.openocd.org/c/openocd/+/7864 Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Walter Ji
committed by
Antonio Borneo
Antonio Borneo
parent
c7d1f0ddab
commit
18c64af135
@@ -823,9 +823,13 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
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return retval;
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}
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int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
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int mips32_pracc_write_regs(struct mips32_common *mips32)
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{
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
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uint32_t *gprs = mips32->core_regs.gpr;
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uint32_t *c0rs = mips32->core_regs.cp0;
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pracc_queue_init(&ctx);
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uint32_t cp0_write_code[] = {
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@@ -837,66 +841,178 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
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MIPS32_MTC0(ctx.isa, 1, 24, 0), /* move $1 to depc (pc) */
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};
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uint32_t cp0_write_data[] = {
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/* lo */
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gprs[32],
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/* hi */
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gprs[33],
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/* status */
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c0rs[0],
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/* badvaddr */
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c0rs[1],
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/* cause */
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c0rs[2],
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/* depc (pc) */
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c0rs[3],
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};
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for (size_t i = 0; i < ARRAY_SIZE(cp0_write_code); i++) {
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/* load CP0 value in $1 */
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pracc_add_li32(&ctx, 1, cp0_write_data[i], 0);
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/* write value from $1 to CP0 register */
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pracc_add(&ctx, 0, cp0_write_code[i]);
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}
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/* load registers 2 to 31 with li32, optimize */
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for (int i = 2; i < 32; i++)
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pracc_add_li32(&ctx, i, regs[i], 1);
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pracc_add_li32(&ctx, i, gprs[i], 1);
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for (int i = 0; i != 6; i++) {
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pracc_add_li32(&ctx, 1, regs[i + 32], 0); /* load CPO value in $1 */
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pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */
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}
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pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); /* load $15 in DeSave */
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pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((regs[1])))); /* load upper half word in $1 */
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pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */
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/* load $15 in DeSave */
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pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
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/* load upper half word in $1 */
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pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((gprs[1]))));
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/* jump to start */
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pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
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/* load lower half word in $1 */
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pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((gprs[1]))));
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
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ejtag_info->reg8 = regs[8];
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ejtag_info->reg9 = regs[9];
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ejtag_info->reg8 = gprs[8];
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ejtag_info->reg9 = gprs[9];
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pracc_queue_free(&ctx);
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return ctx.retval;
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}
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int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
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/* Saves content in `$1` to `DeSave(cp0.31.0)` and loads `MIPS32_PRACC_BASE_ADDR` into `$1` */
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static void mips32_pracc_store_regs_set_base_addr(struct pracc_queue_info *ctx)
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{
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struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
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pracc_queue_init(&ctx);
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/* move $1 to COP0 DeSave */
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pracc_add(ctx, 0, MIPS32_MTC0(ctx->isa, 1, 31, 0));
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/* $1 = MIP32_PRACC_BASE_ADDR */
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pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, 1, PRACC_UPPER_BASE_ADDR));
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}
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uint32_t cp0_read_code[] = {
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MIPS32_MFC0(ctx.isa, 8, 12, 0), /* move status to $8 */
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MIPS32_MFLO(ctx.isa, 8), /* move lo to $8 */
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MIPS32_MFHI(ctx.isa, 8), /* move hi to $8 */
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MIPS32_MFC0(ctx.isa, 8, 8, 0), /* move badvaddr to $8 */
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MIPS32_MFC0(ctx.isa, 8, 13, 0), /* move cause to $8 */
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MIPS32_MFC0(ctx.isa, 8, 24, 0), /* move depc (pc) to $8 */
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/* This function assumes the address for saving is stored in `$1`.
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* And that action is performed in `mips32_pracc_set_save_base_addr`.
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*/
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static void mips32_pracc_store_regs_gpr(struct pracc_queue_info *ctx, unsigned int offset_gpr)
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{
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for (int i = 2; i != 32; i++)
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pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + offset_gpr + (i * 4),
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MIPS32_SW(ctx->isa, i, PRACC_OUT_OFFSET + offset_gpr + (i * 4), 1));
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}
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static void mips32_pracc_store_regs_lohi(struct pracc_queue_info *ctx)
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{
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uint32_t lohi_read_code[] = {
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MIPS32_MFLO(ctx->isa, 8), /* move lo to $8 */
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MIPS32_MFHI(ctx->isa, 8), /* move hi to $8 */
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};
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pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 1, 31, 0)); /* move $1 to COP0 DeSave */
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pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */
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for (int i = 2; i != 32; i++) /* store GPR's 2 to 31 */
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pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i * 4),
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MIPS32_SW(ctx.isa, i, PRACC_OUT_OFFSET + (i * 4), 1));
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for (int i = 0; i != 6; i++) {
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pracc_add(&ctx, 0, cp0_read_code[i]); /* load COP0 needed registers to $8 */
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pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, /* store $8 at PARAM OUT */
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MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
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/* store lo & hi */
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for (int i = 0; i < 2; i++) {
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/* load COP0 needed registers to $8 */
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pracc_add(ctx, 0, lohi_read_code[i]);
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/* store $8 at PARAM OUT */
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pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4,
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MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
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}
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pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 31, 0)); /* move DeSave to $8, reg1 value */
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pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + 4, /* store reg1 value from $8 to param out */
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MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + 4, 1));
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}
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pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */
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pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
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pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); /* load $15 in DeSave */
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/* Saves CP0 registers [status, badvaddr, cause, depc] */
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static void mips32_pracc_store_regs_cp0_context(struct pracc_queue_info *ctx, unsigned int offset_cp0)
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{
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uint32_t cp0_read_code[] = {
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MIPS32_MFC0(ctx->isa, 8, 12, 0), /* move status to $8 */
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MIPS32_MFC0(ctx->isa, 8, 8, 0), /* move badvaddr to $8 */
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MIPS32_MFC0(ctx->isa, 8, 13, 0), /* move cause to $8 */
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MIPS32_MFC0(ctx->isa, 8, 24, 0), /* move depc (pc) to $8 */
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};
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs, 1);
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/* store cp0 */
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for (size_t i = 0; i < ARRAY_SIZE(cp0_read_code); i++) {
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size_t offset = offset_cp0 + (i * 4);
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/* load COP0 needed registers to $8 */
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pracc_add(ctx, 0, cp0_read_code[i]);
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/* store $8 at PARAM OUT */
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pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + offset,
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MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + offset, 1));
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}
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}
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/* Loads original content of $1 into $8,
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* then store it to the batch data access address.
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* Finally it restores $1 from DeSave.
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*/
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static void mips32_pracc_store_regs_restore(struct pracc_queue_info *ctx)
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{
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/* move DeSave to $8, reg1 value */
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pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 8, 31, 0));
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/* store reg1 value from $8 to param out */
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pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + 4,
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MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + 4, 1));
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/* move COP0 DeSave to $1, restore reg1 */
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pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 1, 31, 0));
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}
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/* This function performs following actions:
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* Saves `$1` to `DeSave`,
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* then load `PRACC_UPPER_BASE_ADDR` for saving the register data structure into `$1`,
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* Saves `$2` ~ `$31` to `PRACC_UPPER_BASE_ADDR + offset_gpr`
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* Saves HI and LO,
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* Saves necessary cp0 registers.
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*/
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static void mips32_pracc_store_regs(struct pracc_queue_info *ctx,
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unsigned int offset_gpr, unsigned int offset_cp0)
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{
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mips32_pracc_store_regs_set_base_addr(ctx);
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mips32_pracc_store_regs_gpr(ctx, offset_gpr);
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mips32_pracc_store_regs_lohi(ctx);
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mips32_pracc_store_regs_cp0_context(ctx, offset_cp0);
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mips32_pracc_store_regs_restore(ctx);
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}
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int mips32_pracc_read_regs(struct mips32_common *mips32)
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{
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struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
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struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
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struct mips32_core_regs *core_regs = &mips32->core_regs;
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unsigned int offset_gpr = ((uint8_t *)&core_regs->gpr[0]) - (uint8_t *)core_regs;
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unsigned int offset_cp0 = ((uint8_t *)&core_regs->cp0[0]) - (uint8_t *)core_regs;
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/*
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* This procedure has to be in 2 distinctive steps, because we can
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* only know whether FP is enabled after reading CP0.
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*
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* Step 1: Read everything except CP1 stuff
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* Step 2: Read CP1 stuff if FP is implemented
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*/
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pracc_queue_init(&ctx);
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mips32_pracc_store_regs(&ctx, offset_gpr, offset_cp0);
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/* jump to start */
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pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
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/* load $15 in DeSave */
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pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
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ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1);
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ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */
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ejtag_info->reg9 = regs[9];
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pracc_queue_free(&ctx);
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/* reg8 is saved but not restored, next called function should restore it */
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ejtag_info->reg8 = mips32->core_regs.gpr[8];
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ejtag_info->reg9 = mips32->core_regs.gpr[9];
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/* we only care if FP is actually impl'd and if cp1 is enabled */
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/* since we already read cp0 in the prev step */
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/* now we know what's in cp0.status */
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/* TODO: Read FPRs */
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return ctx.retval;
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}
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