auracaster/openocd
3
0
Fork 1
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

- renamed M5960 USB JTAG to "flyswatter"

Browse Source 
- make ep93xx and at91rm9200 bitbang JTAG interfaces dependant on ARM host (thanks to Vincent Palatin)
- various whitespace fixes
- removed various warnings
- add support for Debian GNU/kFreeBSD (thanks to Uwe Hermann)
- fix OpenOCD compilation for various platforms (thanks to Uwe Hermann and Vincent Palatin)
- switched order of JTAG chain examination and validation (examine first, then multiple validation tries even if examination failed)
- added target_request subsystem to handle requests from the target (debug messages and tracepoints implemented, future enhancements might include
semihosting, all ARM7/9 only for now)
- added support for GDB vFlashXXX packets (thanks to Pavel Chromy)
- added support for receiving data via ARM7/9 DCC
- reworked flash writing. the 'flash write' command is now deprecated and replaced by 'flash write_binary' (old syntax and behaviour) and 'flash
write_image' (write image files (bin, hex, elf, s19) to a target).
- added support for AMD/ST/SST 29F400B non-cfi flashes



git-svn-id: svn://svn.berlios.de/openocd/trunk@190 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2007-08-10 19:44:06 +00:00
parent 835e6440b8
commit 20e4e77cdf
58 changed files with 1618 additions and 636 deletions
Download Patch File Download Diff File Expand all files Collapse all files

69
src/target/embeddedice.c
View File

@@ -274,6 +274,75 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
return ERROR_OK;
}
/* receive <size> words of 32 bit from the DCC
* we pretend the target is always going to be fast enough
* (relative to the JTAG clock), so we don't need to handshake
*/
int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
{
u8 reg_addr = 0x5;
scan_field_t fields[3];
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = jtag_info->chain_pos;
fields[1].num_bits = 5;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
fields[1].out_mask = NULL;
fields[1].in_value = NULL;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
fields[2].device = jtag_info->chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
fields[2].in_check_value = NULL;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
while (size > 0)
{
/* when reading the last item, set the register address to the DCC control reg,
* to avoid reading additional data from the DCC data reg
*/
if (size == 1)
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
fields[0].in_handler = arm_jtag_buf_to_u32;
fields[0].in_handler_priv = data;
jtag_add_dr_scan(3, fields, -1, NULL);
data++;
size--;
}
free(fields[1].out_value);
free(fields[2].out_value);
return jtag_execute_queue();
}
int embeddedice_read_reg(reg_t *reg)
{
return embeddedice_read_reg_w_check(reg, NULL, NULL);