target/riscv: tcl/target: move the WA for GD32VF103 to Tcl

The GD32VF103 has a perculiar reset procedure that does not fully comply
with the RISC-V Debug Specification.
Move the workaroung to the `deassert-reset-post` handler.

Change-Id: I153c866a5b7e2dff2552cc92772ce6ed77ad606b
Signed-off-by: Evgeniy Naydanov <eugnay@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/9314
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins

tcl/target/gd32vf103.cfg

@@ -116,6 +116,22 @@ $_TARGETNAME configure -event reset-assert {
 	default_mem_access
 }
 
+# On GD32VF103 the specification's requirement that each hart is in "exactly
+# one of four states" is violated and, during reset, report harts as both
+# unavailable and halted/running. To work around this, after the havereset is
+# lowered in the main deassert_reset procedure, we wait for the absence of the
+# unavailable state.
+$_TARGETNAME configure -event reset-deassert-post {
+	set timeout_s 2
+	set start [clock seconds]
+	# dmstatus address is 0x11, allunavail is the 12th bit
+	while {[riscv dmi_read 0x11] & 1 << 12} {
+		if {[clock seconds] - $start > $timeout_s} {
+			error {Timed out waiting for the hart to become available after a reset}
+		}
+	}
+}
+
 # Capture the mode of a given reset so that we can use it later in the
 # reset-assert handler.
 proc init_reset { mode } {