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target: restructure dap support

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- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
  instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
  longer references the dap, daps are now independently
  created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
  power cycle)
- update documentation
- update target files

Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4468
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Matthias Welwarsky
2018-03-23 21:17:29 +01:00
committed by Matthias Welwarsky
parent 7274090456
commit 2231da8ec4
88 changed files with 1056 additions and 498 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
tcl/target/1986ве1т.cfg
View File

@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } {
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
# use AHB-Lite SRAM for work area
$_TARGETNAME configure -work-area-phys 0x20100000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/adsp-sc58x.cfg
View File

@@ -27,9 +27,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_a -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -event examine-end {
global _TARGETNAME

5
tcl/target/aducm360.cfg
View File

@@ -32,7 +32,8 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x2ba01477
}
swd newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# SWD/JTAG speed
adapter_khz 1000
@@ -41,7 +42,7 @@ adapter_khz 1000
## Target configuration
##
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
# allocate the working area
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

7
tcl/target/altera_fpgasoc.cfg
View File

@@ -14,7 +14,7 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
# Subsidiary TAP: fpga
@@ -42,7 +42,8 @@ set _TARGETNAME1 $_CHIPNAME.cpu.0
set _TARGETNAME2 $_CHIPNAME.cpu.1
# A9 core 0
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap \
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80110000
$_TARGETNAME1 configure -event reset-start { adapter_khz 1000 }
@@ -51,7 +52,7 @@ $_TARGETNAME1 configure -event gdb-attach { halt }
# A9 core 1
#target create $_TARGETNAME2 cortex_a -chain-position $_CHIPNAME.dap \
#target create $_TARGETNAME2 cortex_a -dap $_CHIPNAME.dap \
# -coreid 1 -dbgbase 0x80112000
#$_TARGETNAME2 configure -event reset-start { adapter_khz 1000 }

16
tcl/target/am335x.cfg
View File

@@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } {
if { [info exists DEFAULT_TAPS] } {
set _DEFAULT_TAPS "$DEFAULT_TAPS"
} else {
set _DEFAULT_TAPS "$_CHIPNAME.dap"
set _DEFAULT_TAPS "$_CHIPNAME.tap"
}
#
@@ -23,8 +23,9 @@ if { [info exists DAP_TAPID] } {
} else {
set _DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 12 0"
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
#
# M3 DAP
@@ -34,8 +35,9 @@ if { [info exists M3_DAP_TAPID] } {
} else {
set _M3_DAP_TAPID 0x4b6b902f
}
jtag newtap $_CHIPNAME m3_dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m3_dap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
jtag newtap $_CHIPNAME m3_tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m3_tap -event tap-enable "icepick_d_tapenable $_CHIPNAME.jrc 11 0"
dap create $_CHIPNAME.m3_dap -chain-position $_CHIPNAME.m3_tap
#
# ICEpick-D (JTAG route controller)
@@ -66,13 +68,13 @@ proc enable_default_taps { taps } {
# Cortex-M3 target
#
set _TARGETNAME_2 $_CHIPNAME.m3
target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.m3_dap
target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.m3_dap
#
# Cortex-A8 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80001000
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80001000
# SRAM: 64K at 0x4030.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000

4
tcl/target/am437x.cfg
View File

@@ -458,6 +458,7 @@ if { [info exists M3_DAP_TAPID] } {
}
jtag newtap $_CHIPNAME $M3_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_DAP_TAPID -disable
jtag configure $M3_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 11 0"
dap create $M3_NAME.dap -chain-position $M3_NAME
#
# DebugSS DAP
@@ -469,6 +470,7 @@ if { [info exists DAP_TAPID] } {
}
jtag newtap $_CHIPNAME $DEBUGSS_MODULE -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $DEBUGSS_NAME -event tap-enable "icepick_d_tapenable $JRC_NAME 12 0"
dap create $DEBUGSS_NAME.dap -chain-position $DEBUGSS_NAME
#
# ICEpick-D (JTAG route controller)
@@ -486,7 +488,7 @@ jtag configure $JRC_NAME -event post-reset "runtest 100"
#
# Cortex-A9 target
#
target create $_TARGETNAME cortex_a -chain-position $DEBUGSS_NAME -coreid 0 -dbgbase 0x80000000
target create $_TARGETNAME cortex_a -dap $DEBUGSS_NAME.dap -coreid 0 -dbgbase 0x80000000
# SRAM: 256K at 0x4030.0000

7
tcl/target/amdm37x.cfg
View File

@@ -86,8 +86,8 @@ source [find target/icepick.cfg]
# Secondary TAP: DAP is closest to the TDO output
# The TAP enable event also needs to be described
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# These taps are only present in the DM37x series.
@@ -141,7 +141,8 @@ jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
# Create the CPU target to be used with GDB: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# The DM37x has 64K of SRAM starting at address 0x4020_0000. Allow the first
# 16K to be used as a scratchpad for OpenOCD.

5
tcl/target/armada370.cfg
View File

@@ -16,10 +16,11 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
proc armada370_dbginit {target} {
cortex_a dbginit

3
tcl/target/at91sam3XXX.cfg
View File

@@ -55,9 +55,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
# 16K is plenty, the smallest chip has this much
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/at91sam3nXX.cfg
View File

@@ -18,9 +18,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
set _FLASHNAME $_CHIPNAME.flash
flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME

3
tcl/target/at91sam4XXX.cfg
View File

@@ -35,9 +35,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
# 16K is plenty, the smallest chip has this much
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/at91samdXX.cfg
View File

@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/atsamv.cfg
View File

@@ -32,9 +32,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20400000 -work-area-size $_WORKAREASIZE -work-area-backup 0

8
tcl/target/bcm281xx.cfg
View File

@@ -14,15 +14,17 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -expected-id $_DAP_TAPID -irlen 4
jtag newtap $_CHIPNAME cpu -expected-id $_DAP_TAPID -irlen 4
# Dual Cortex-A9
set _TARGETNAME0 $_CHIPNAME.cpu0
set _TARGETNAME1 $_CHIPNAME.cpu1
target create $_TARGETNAME0 cortex_a -chain-position $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
target create $_TARGETNAME1 cortex_a -chain-position $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME0 cortex_a -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x3fe10000
target create $_TARGETNAME1 cortex_a -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x3fe12000
target smp $_TARGETNAME0 $_TARGETNAME1
$_TARGETNAME0 configure -event gdb-attach {

3
tcl/target/bluenrg-x.cfg
View File

@@ -29,12 +29,13 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
set WDOG_VALUE 0
set WDOG_VALUE_SET 0
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000100 -work-area-size $_WORKAREASIZE -work-area-backup 0

9
tcl/target/cc26xx.cfg
View File

@@ -19,8 +19,8 @@ if { [info exists DAP_TAPID] } {
} else {
set _DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
#
# ICEpick-C (JTAG route controller)
@@ -33,11 +33,12 @@ if { [info exists JRC_TAPID] } {
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
# A start sequence is needed to change from cJTAG (Compact JTAG) to
# 4-pin JTAG before talking via JTAG commands
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
#
# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap

9
tcl/target/cc32xx.cfg
View File

@@ -26,10 +26,10 @@ if { [info exists DAP_TAPID] } {
}
if {[using_jtag]} {
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
} else {
swj_newdap $_CHIPNAME dap -expected-id $_DAP_TAPID
swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
}
#
@@ -50,4 +50,5 @@ if {[using_jtag]} {
# Cortex-M3 target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.dap
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap

3
tcl/target/efm32.cfg
View File

@@ -32,11 +32,12 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
adapter_khz 1000
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/em357.cfg
View File

@@ -50,12 +50,13 @@ if { [info exists FLASHSIZE] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if { [using_jtag] } {
swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

5
tcl/target/exynos5250.cfg
View File

@@ -17,7 +17,8 @@ if { [info exists CPUTAPID] } {
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -chain-position $_TARGETNAME
target create ${_TARGETNAME}1 cortex_a -chain-position $_TARGETNAME
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap
target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap
target smp ${_TARGETNAME}0 ${_TARGETNAME}1

3
tcl/target/fm3.cfg
View File

@@ -31,9 +31,10 @@ if {[using_jtag]} {
reset_config trst_only
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
# MB9BF506 has 64kB of SRAM on its main system bus
$_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0

3
tcl/target/fm4.cfg
View File

@@ -19,9 +19,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
adapter_khz 500

6
tcl/target/hi3798.cfg
View File

@@ -16,8 +16,8 @@ if { [info exists DAP_TAPID] } {
}
# declare the one JTAG tap to access the DAP
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# declare the 4 main application cores
set _TARGETNAME $_CHIPNAME.cpu
set _smp_command ""
@@ -33,7 +33,7 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
set _command "target create ${_TARGETNAME}$_core aarch64 \
-chain-position $_CHIPNAME.dap -coreid $_core -ctibase [set $_TARGETNAME.cti($_core)]"
-dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
if { $_core != 0 } {
# non-boot core examination may fail

15
tcl/target/hi6220.cfg
View File

@@ -16,7 +16,10 @@ if { [info exists DAP_TAPID] } {
}
# declare the one JTAG tap to access the DAP
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version
# create the DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
# declare the 8 main application cores
set _TARGETNAME $_CHIPNAME.cpu
@@ -34,10 +37,10 @@ set $_TARGETNAME.cti(7) 0x801DB000
set _cores 8
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
cti create cti$_core -chain-position $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
set _command "target create ${_TARGETNAME}$_core aarch64 \
-chain-position $_CHIPNAME.dap -coreid $_core -cti cti$_core"
-dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
if { $_core != 0 } {
# non-boot core examination may fail
@@ -54,10 +57,10 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
eval $_smp_command
cti create cti.sys -chain-position hi6220.dap -ap-num 0 -ctibase 0x80003000
cti create cti.sys -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0x80003000
# declare the auxiliary Cortex-M3 core on AP #2 (runs mcuimage.bin)
target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 2 -defer-examine
target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
# declare the auxiliary Cortex-A7 core
target create ${_TARGETNAME}.a7 cortex_a -chain-position $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine
target create ${_TARGETNAME}.a7 cortex_a -dap $_CHIPNAME.dap -dbgbase 0x80210000 -defer-examine

11
tcl/target/imx51.cfg
View File

@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x1ba00477
}
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
# SJC
if { [info exists SJC_TAPID] } {
@@ -26,15 +26,16 @@ if { [info exists SJC_TAPID] } {
set _SJC_TAPID 0x0190c01d
}
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
-expected-id $_SJC_TAPID -ignore-version
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
proc imx51_dbginit {target} {
# General Cortex-A8 debug initialisation

11
tcl/target/imx53.cfg
View File

@@ -13,11 +13,11 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x1ba00477
}
jtag newtap $_CHIPNAME DAP -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID
# SDMA / no IDCODE
jtag newtap $_CHIPNAME SDMA -irlen 4 -ircapture 0x0 -irmask 0xf
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x0 -irmask 0xf
# SJC
if { [info exists SJC_TAPID] } {
@@ -26,15 +26,16 @@ if { [info exists SJC_TAPID] } {
set _SJC_TAPID 0x0190d01d
}
jtag newtap $_CHIPNAME SJC -irlen 5 -ircapture 0x1 -irmask 0x1f \
jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x1 -irmask 0x1f \
-expected-id $_SJC_TAPID -ignore-version
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# some TCK tycles are required to activate the DEBUG power domain
jtag configure $_CHIPNAME.SJC -event post-reset "runtest 100"
jtag configure $_CHIPNAME.sjc -event post-reset "runtest 100"
proc imx53_dbginit {target} {
# General Cortex-A8 debug initialisation

5
tcl/target/imx6.cfg
View File

@@ -13,7 +13,7 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
# SDMA / no IDCODE
@@ -40,7 +40,8 @@ jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
# core 2 - 0x82154000
# core 3 - 0x82156000
set _TARGETNAME $_CHIPNAME.cpu.0
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x82150000
# some TCK cycles are required to activate the DEBUG power domain

11
tcl/target/imx7.cfg
View File

@@ -11,7 +11,7 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x5ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
-expected-id $_DAP_TAPID
#
@@ -22,16 +22,19 @@ jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
# core 0 - 0x80070000
# core 1 - 0x80072000
set _TARGETNAME $_CHIPNAME.cpu_a7
target create $_TARGETNAME.0 cortex_a -chain-position $_CHIPNAME.dap \
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80070000
target create $_TARGETNAME.1 cortex_a -chain-position $_CHIPNAME.dap \
target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap \
-coreid 1 -dbgbase 0x80072000 -defer-examine
#
# Cortex-M4 target
#
set _TARGETNAME_2 $_CHIPNAME.cpu_m4
target create $_TARGETNAME_2 cortex_m -chain-position $_CHIPNAME.dap -ap-num 4 \
target create $_TARGETNAME_2 cortex_m -dap $_CHIPNAME.dap -ap-num 4 \
-defer-examine
targets $_TARGETNAME.0

3
tcl/target/k1921vk01t.cfg
View File

@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } {
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/ke0x.cfg
View File

@@ -25,9 +25,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/klx.cfg
View File

@@ -26,9 +26,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/kx.cfg
View File

@@ -30,9 +30,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/lpc1850.cfg
View File

@@ -23,9 +23,10 @@ if { [info exists M3_JTAG_TAPID] } {
}
swj_newdap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.m3
set _TARGETNAME $_CHIPNAME.m3
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to

3
tcl/target/lpc1xxx.cfg
View File

@@ -75,9 +75,10 @@ if { [info exists WORKAREASIZE] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
# The LPC11xx devices have 2/4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)
# The LPC12xx devices have 4/8kB of SRAM in the ARMv7-M "Code" area (at 0x10000000)

6
tcl/target/lpc4350.cfg
View File

@@ -43,12 +43,14 @@ if { [info exists M0_JTAG_TAPID] } {
swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M4_TAPID
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
if { [using_jtag] } {
swj_newdap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M0_JTAG_TAPID
target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0
dap create $_CHIPNAME.m0.dap -chain-position $_CHIPNAME.m0
target create $_CHIPNAME.m0 cortex_m -dap $_CHIPNAME.m0.dap
}
# LPC4350 has 96+32 KB SRAM

10
tcl/target/lpc4370.cfg
View File

@@ -47,8 +47,8 @@ if { [info exists M0_JTAG_TAPID] } {
swj_newdap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M4_TAPID
target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4
dap create $_CHIPNAME.m4.dap -chain-position $_CHIPNAME.m4
target create $_CHIPNAME.m4 cortex_m -dap $_CHIPNAME.m4.dap
# LPC4370 has 96+32 KB contiguous SRAM
if { [info exists WORKAREASIZE] } {
@@ -65,8 +65,10 @@ if { [using_jtag] } {
jtag newtap $_CHIPNAME m0sub -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M0_JTAG_TAPID
target create $_CHIPNAME.m0app cortex_m -chain-position $_CHIPNAME.m0app
target create $_CHIPNAME.m0sub cortex_m -chain-position $_CHIPNAME.m0sub
dap create $_CHIPNAME.m0app.dap -chain-position $_CHIPNAME.m0app
dap create $_CHIPNAME.m0sub.dap -chain-position $_CHIPNAME.m0sub
target create $_CHIPNAME.m0app cortex_m -dap $_CHIPNAME.m0app.dap
target create $_CHIPNAME.m0sub cortex_m -dap $_CHIPNAME.m0sub.dap
# 32+8+32 KB SRAM
$_CHIPNAME.m0app configure -work-area-phys 0x10080000 \

9
tcl/target/marvell/88f37x0.cfg
View File

@@ -35,7 +35,8 @@ if { [info exists DAP_TAPID] } {
}
# declare the one JTAG tap to access the DAP
swj_newdap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -ignore-version -enable
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# declare the main application cores
set _TARGETNAME $_CHIPNAME.cpu
@@ -43,10 +44,10 @@ set _smp_command ""
for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
cti create cti$_core -chain-position $_CHIPNAME.dap -ctibase [lindex $_ctis $_core] -ap-num 0
cti create cti$_core -dap $_CHIPNAME.dap -ctibase [lindex $_ctis $_core] -ap-num 0
set _command "target create ${_TARGETNAME}$_core aarch64 \
-chain-position $_CHIPNAME.dap -coreid $_core \
-dap $_CHIPNAME.dap -coreid $_core \
-cti cti$_core"
if { $_core != 0 } {
@@ -65,6 +66,6 @@ for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
eval $_smp_command
# declare the auxiliary Cortex-M3 core on AP #3
target create ${_TARGETNAME}.m3 cortex_m -chain-position $_CHIPNAME.dap -ap-num 3 -defer-examine
target create ${_TARGETNAME}.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
targets ${_TARGETNAME}0

3
tcl/target/mdr32f9q2i.cfg
View File

@@ -34,9 +34,10 @@ if { [info exists CPUTAPID] } {
}
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/nrf51.cfg
View File

@@ -31,9 +31,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/nrf52.cfg
View File

@@ -25,9 +25,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
adapter_khz 1000

3
tcl/target/numicro.cfg
View File

@@ -28,8 +28,9 @@ if { [info exists WORKAREASIZE] } {
# Debug Adapter Target Settings
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUDAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

7
tcl/target/omap3530.cfg
View File

@@ -20,9 +20,9 @@ if { [info exists DAP_TAPID] } {
} else {
set _DAP_TAPID 0x0b6d602f
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
# Primary TAP: ICEpick-C (JTAG route controller) and boundary scan
@@ -36,7 +36,8 @@ jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
# GDB target: Cortex-A8, using DAP
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap
# SRAM: 64K at 0x4020.0000; use the first 16K
$_TARGETNAME configure -work-area-phys 0x40200000 -work-area-size 0x4000

30
tcl/target/omap4430.cfg
View File

@@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x3BA00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 9"
@@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } {
set _M3_DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m31_dap -event tap-enable \
jtag configure $_CHIPNAME.m31 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 5"
jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m30_dap -event tap-enable \
jtag configure $_CHIPNAME.m30 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 4"
@@ -93,8 +93,9 @@ set _TARGETNAME $_CHIPNAME.cpu
set _coreid 0
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
echo "Using dbgbase = [format 0x%x $_dbgbase]"
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase $_dbgbase
# SRAM: 56KiB at 0x4030.0000
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
#
# M3 targets, separate TAP/DAP for each core
#
target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
# Once the JRC is up, enable our TAPs
jtag configure $_CHIPNAME.jrc -event setup "
jtag tapenable $_CHIPNAME.dap
jtag tapenable $_CHIPNAME.m30_dap
jtag tapenable $_CHIPNAME.m31_dap
jtag tapenable $_CHIPNAME.cpu
jtag tapenable $_CHIPNAME.m30
jtag tapenable $_CHIPNAME.m31
"
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset
@@ -124,4 +127,3 @@ $_CHIPNAME.m31 configure -event reset-assert { }
# Soft breakpoints don't currently work due to broken cache handling
gdb_breakpoint_override hard

27
tcl/target/omap4460.cfg
View File

@@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x3BA00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_DAP_TAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
jtag configure $_CHIPNAME.cpu -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 9"
@@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } {
set _M3_DAP_TAPID 0x4BA00477
}
jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m31_dap -event tap-enable \
jtag configure $_CHIPNAME.m31 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 5"
jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \
jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \
-expected-id $_M3_DAP_TAPID -disable
jtag configure $_CHIPNAME.m30_dap -event tap-enable \
jtag configure $_CHIPNAME.m30 -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 4"
@@ -94,7 +94,8 @@ set _coreid 0
set _dbgbase [expr 0x80000000 | ($_coreid << 13)]
echo "Using dbgbase = [format 0x%x $_dbgbase]"
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase $_dbgbase
# SRAM: 56KiB at 0x4030.0000
@@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000
#
# M3 targets, separate TAP/DAP for each core
#
target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap
dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30
dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31
target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap
target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap
# Once the JRC is up, enable our TAPs
jtag configure $_CHIPNAME.jrc -event setup "
jtag tapenable $_CHIPNAME.dap
jtag tapenable $_CHIPNAME.m30_dap
jtag tapenable $_CHIPNAME.m31_dap
jtag tapenable $_CHIPNAME.cpu
jtag tapenable $_CHIPNAME.m30
jtag tapenable $_CHIPNAME.m31
"
# Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset

3
tcl/target/psoc4.cfg
View File

@@ -26,9 +26,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/psoc5lp.cfg
View File

@@ -23,9 +23,10 @@ if { [using_jtag] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_DAP_ID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if {![using_hla]} {
cortex_m reset_config sysresetreq

5
tcl/target/psoc6.cfg
View File

@@ -19,6 +19,7 @@ global TARGET
set TARGET $_CHIPNAME.cpu
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
# Is CM0 Debugging enabled ?
global _ENABLE_CM0
@@ -99,7 +100,7 @@ proc psoc6_deassert_post { target } {
}
if { $_ENABLE_CM0 } {
target create ${TARGET}.cm0 cortex_m -chain-position $TARGET -ap-num 1 -coreid 0
target create ${TARGET}.cm0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
${TARGET}.cm0 configure -work-area-phys $_WORKAREAADDR_CM0 -work-area-size $_WORKAREASIZE_CM0 -work-area-backup 0
flash bank main_flash_cm0 psoc6 0x10000000 0 0 0 ${TARGET}.cm0
@@ -114,7 +115,7 @@ if { $_ENABLE_CM0 } {
}
if { $_ENABLE_CM4 } {
target create ${TARGET}.cm4 cortex_m -chain-position $TARGET -ap-num 2 -coreid 1
target create ${TARGET}.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
${TARGET}.cm4 configure -work-area-phys $_WORKAREAADDR_CM4 -work-area-size $_WORKAREASIZE_CM4 -work-area-backup 0
flash bank main_flash_cm4 psoc6 0x10000000 0 0 0 ${TARGET}.cm4

3
tcl/target/renesas_s7g2.cfg
View File

@@ -29,9 +29,10 @@ if { [using_jtag] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE

3
tcl/target/sim3x.cfg
View File

@@ -38,9 +38,10 @@ if { [info exists WORKAREASIZE] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE

5
tcl/target/stellaris.cfg
View File

@@ -42,7 +42,8 @@ if { [info exists CPUTAPID] } {
# ... even though SWD ignores all except TAPID, and
# JTAG shouldn't need anything more then irlen. (and TAPID).
swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
-expected-id $_CPUTAPID -ignore-version
-expected-id $_CPUTAPID -ignore-version
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
@@ -52,7 +53,7 @@ if { [info exists WORKAREASIZE] } {
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
# 8K working area at base of ram, not backed up
#

3
tcl/target/stm32f0x.cfg
View File

@@ -32,9 +32,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32f1x.cfg
View File

@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32f2x.cfg
View File

@@ -49,13 +49,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32f3x.cfg
View File

@@ -49,13 +49,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32f4x.cfg
View File

@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32f7x.cfg
View File

@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32h7x.cfg
View File

@@ -34,13 +34,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
swj_newdap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32l0.cfg
View File

@@ -37,9 +37,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32l1.cfg
View File

@@ -45,13 +45,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32l4x.cfg
View File

@@ -36,13 +36,14 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
jtag newtap $_CHIPNAME bs -irlen 5
}
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/stm32w108xx.cfg
View File

@@ -37,6 +37,7 @@ if { [info exists CPUTAPID] } {
set _ENDIAN little
swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
if {[using_jtag]} {
if { [info exists BSTAPID] } {
@@ -53,7 +54,7 @@ if {[using_jtag]} {
# Set Target
#
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

3
tcl/target/ti_msp432p4xx.cfg
View File

@@ -31,9 +31,10 @@ if { [using_jtag] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE

16
tcl/target/u8500.cfg
View File

@@ -167,11 +167,11 @@ if { [info exists CPUTAPID] } {
} else {
set _CPUTAPID 0x4ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
jtag configure $_CHIPNAME.dap -event tap-enable \
"u8500_dapenable $_CHIPNAME.dap"
jtag configure $_CHIPNAME.dap -event tap-disable \
"u8500_tapdisable $_CHIPNAME.dap 0xc0"
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_CPUTAPID -disable
jtag configure $_CHIPNAME.cpu -event tap-enable \
"u8500_dapenable $_CHIPNAME.cpu"
jtag configure $_CHIPNAME.cpu -event tap-disable \
"u8500_tapdisable $_CHIPNAME.cpu 0xc0"
#CLTAPC TAP JRC equivalent
@@ -202,7 +202,9 @@ if { [info exists DAP_DBG2] } {
set _DAP_DBG2 0x801AA000
}
target create $_TARGETNAME_1 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create $_TARGETNAME_1 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG1 -coreid 0 -rtos linux
$_TARGETNAME_1 configure -event gdb-attach {
halt
@@ -217,7 +219,7 @@ global _TARGETNAME_2
set _TARGETNAME_2 $TARGETNAME_2
}
target create $_TARGETNAME_2 cortex_a -chain-position $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
target create $_TARGETNAME_2 cortex_a -dap $_CHIPNAME.dap -dbgbase $_DAP_DBG2 -coreid 1 -rtos linux
$_TARGETNAME_2 configure -event gdb-attach {
halt

3
tcl/target/vybrid_vf6xx.cfg
View File

@@ -29,8 +29,9 @@ if { [using_jtag] } {
source [find target/swj-dp.tcl]
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_A5_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.cpu -dbgbase 0xc0088000
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap -dbgbase 0xc0088000
adapter_khz 1000

8
tcl/target/xilinx_ultrascale.cfg
View File

@@ -17,7 +17,8 @@ if { [info exists DAP_TAPID] } {
set _DAP_TAPID 0x5ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
jtag newtap $_CHIPNAME tap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
#
# PS tap
@@ -53,6 +54,7 @@ jtag configure $_CHIPNAME.ps -event setup {
set _TARGETNAME $_CHIPNAME.a53
set _CTINAME $_CHIPNAME.cti
set _smp_command ""
set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
@@ -60,10 +62,10 @@ set _cores 4
for { set _core 0 } { $_core < $_cores } { incr _core } {
cti create $_CTINAME.$_core -chain-position $_CHIPNAME.dap -ap-num 1 \
cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
-ctibase [lindex $CTIBASE $_core]
set _command "target create $_TARGETNAME.$_core aarch64 -chain-position $_CHIPNAME.dap \
set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
-dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
if { $_core != 0 } {

3
tcl/target/xmc1xxx.cfg
View File

@@ -20,9 +20,10 @@ if { [info exists CPUTAPID] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_SWD_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE

3
tcl/target/xmc4xxx.cfg
View File

@@ -35,9 +35,10 @@ if { [using_jtag] } {
}
swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPU_TAPID
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
# Work-area is a space in RAM used for flash programming
# By default use 16 kB

8
tcl/target/zynq_7000.cfg
View File

@@ -13,11 +13,13 @@ jtag newtap zynq_pl bs -irlen 6 -ircapture 0x1 -irmask 0x03 \
-expected-id 0x03727093 \
-expected-id 0x03736093
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x4ba00477
target create ${_TARGETNAME}0 cortex_a -chain-position $_CHIPNAME.dap \
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
target create ${_TARGETNAME}0 cortex_a -dap $_CHIPNAME.dap \
-coreid 0 -dbgbase 0x80090000
target create ${_TARGETNAME}1 cortex_a -chain-position $_CHIPNAME.dap \
target create ${_TARGETNAME}1 cortex_a -dap $_CHIPNAME.dap \
-coreid 1 -dbgbase 0x80092000
target smp ${_TARGETNAME}0 ${_TARGETNAME}1