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ADIv5 clean up AP selection and register caching

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Handling of AP (and AP register bank) selection, and cached AP
registers, is pretty loose ... start tightening it:

 - It's "AP bank" select support ... there are no DP banks.  Rename.
   + dap_dp_bankselect() becomes dap_ap_bankselect()
   + "dp_select_value" struct field becomes "ap_bank_value"

 - Remove duplicate AP cache init paths ... only use dap_ap_select(),
 and don't make Cortex (A8 or M3) cores roll their own code.

 - For dap_ap_bankselect(), pass up any fault code from writing
 the SELECT register.  (Nothing yet checks those codes.)

 - Add various bits of Doxygen

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2010-02-21 14:48:04 -08:00
parent 1aac72d243
commit 249263d29d
4 changed files with 60 additions and 34 deletions
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8
src/target/cortex_a8.c
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@@ -53,7 +53,9 @@ static int cortex_a8_dap_write_coreregister_u32(struct target *target,
uint32_t value, int regnum);
/*
* FIXME do topology discovery using the ROM; don't
* assume this is an OMAP3.
* assume this is an OMAP3. Also, allow for multiple ARMv7-A
* cores, with different AP numbering ... don't use a #define
* for these numbers, use per-core armv7a state.
*/
#define swjdp_memoryap 0
#define swjdp_debugap 1
@@ -1570,9 +1572,7 @@ static int cortex_a8_init_arch_info(struct target *target,
cortex_a8->jtag_info.tap = tap;
cortex_a8->jtag_info.scann_size = 4;
swjdp->dp_select_value = -1;
swjdp->ap_csw_value = -1;
swjdp->ap_tar_value = -1;
/* Leave (only) generic DAP stuff for debugport_init() */
swjdp->jtag_info = &cortex_a8->jtag_info;
swjdp->memaccess_tck = 80;