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ADIv5: use new dap_run() operation

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Make ADIv5 use one of the new transport-neutral interfaces: call
dap_run(), not jtagdp_transaction_endcheck().

Also, make that old interface private; and bugfix some of its call
sites to handle the fault returns, instead of ignoring them.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2010-03-02 22:42:45 -08:00
parent db6c994642
commit 24b1426a72
3 changed files with 74 additions and 37 deletions
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23
src/target/cortex_m3.c
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@@ -78,7 +78,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
retval = jtagdp_transaction_endcheck(swjdp);
retval = dap_run(swjdp);
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
@@ -107,7 +107,7 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
retval = jtagdp_transaction_endcheck(swjdp);
retval = dap_run(swjdp);
/* restore DCB_DCRDR - this needs to be in a seperate
* transaction otherwise the emulated DCC channel breaks */
@@ -179,6 +179,7 @@ static int cortex_m3_single_step_core(struct target *target)
static int cortex_m3_endreset_event(struct target *target)
{
int i;
int retval;
uint32_t dcb_demcr;
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
@@ -234,14 +235,16 @@ static int cortex_m3_endreset_event(struct target *target)
target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
dwt_list[i].function);
}
jtagdp_transaction_endcheck(swjdp);
retval = dap_run(swjdp);
if (retval != ERROR_OK)
return retval;
register_cache_invalidate(cortex_m3->armv7m.core_cache);
/* make sure we have latest dhcsr flags */
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
return ERROR_OK;
return retval;
}
static int cortex_m3_examine_debug_reason(struct target *target)
@@ -276,6 +279,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
uint32_t shcsr, except_sr, cfsr = -1, except_ar = -1;
struct armv7m_common *armv7m = target_to_armv7m(target);
struct swjdp_common *swjdp = &armv7m->swjdp_info;
int retval;
mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
switch (armv7m->exception_number)
@@ -313,10 +317,13 @@ static int cortex_m3_examine_exception_reason(struct target *target)
except_sr = 0;
break;
}
jtagdp_transaction_endcheck(swjdp);
LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
shcsr, except_sr, cfsr, except_ar);
return ERROR_OK;
retval = dap_run(swjdp);
if (retval == ERROR_OK)
LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
armv7m_exception_string(armv7m->exception_number),
shcsr, except_sr, cfsr, except_ar);
return retval;
}
/* PSP is used in some thread modes */