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tcl: fix some minor typo

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Minor typos found by the new checkpatch boosted by the dictionary
provided by 'codespell'.
While there, fix one indentation.

Change-Id: I72369ed26f363bacd760b40b8c83dd95e89d28a4
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6214
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2021-01-28 12:27:53 +01:00
parent f440af41ff
commit 2a1f3b2574
13 changed files with 18 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tcl/target/c100config.tcl
+3 -3
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@@ -43,7 +43,7 @@ proc setupTelo {} {
# setup GPIO used as control signals for C100
setupGPIO
# This will allow acces to lower 8MB or NOR
# This will allow access to lower 8MB or NOR
lowGPIO5
# setup NOR size,timing,etc.
setupNOR
@@ -79,7 +79,7 @@ proc setupNOR {} {
#mww $EX_CS0_TMG3_REG
# set EBUS clock 165/5=33MHz
mww $EX_CLOCK_DIV_REG 0x5
# everthing else is OK with default
# everything else is OK with default
}
proc bootNOR {} {
@@ -159,7 +159,7 @@ proc boardID {id} {
proc ooma_board_detect {} {
set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
# read the current value of the BOOTSRAP pins
# read the current value of the BOOTSTRAP pins
set tmp [mrw $GPIO_BOOTSTRAP_REG]
echo [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
# extract the GPBP bits
tcl/target/c100helper.tcl
+4 -4
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@@ -13,16 +13,16 @@ proc helpC100 {} {
echo "10) showArmClk: will show current config registers for Arm Bus Clock"
echo "11) setupArmClk: will setup Amba Bus Clock=450MHz"
echo "12) ooma_board_detect: will show which version of Telo you have"
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
echo "13) setupDDR2: will configure DDR2 controller, you must have PLLs configured"
echo "14) showDDR2: will show DDR2 config registers"
echo "15) showWatchdog: will show current register config for watchdog"
echo "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
echo "17) bootNOR: will boot Telo from NOR"
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
echo "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be configured"
echo "19) putcUART0: will print a character on UART0"
echo "20) putsUART0: will print a string on UART0"
echo "21) trainDDR2: will run DDR2 training program"
echo "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
echo "21) trainDDR2: will run DDR2 training program"
echo "22) flashUBOOT: will program NOR sectors 0-3 with u-boot.bin"
}
source [find mem_helper.tcl]
tcl/target/davinci.cfg
+1 -1
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@@ -267,7 +267,7 @@ proc pll_v03_setup {pll_addr mult config} {
if {$aln != 0} {
# clear pllcmd.GO
mww [expr {$pll_addr + 0x0138}] 0x00
# write alingment flags
# write alignment flags
mww [expr {$pll_addr + 0x0140}] $aln
# write pllcmd.GO; poll pllstat.GO
mww [expr {$pll_addr + 0x0138}] 0x01
tcl/target/lpc8nxx.cfg
+1 -1
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@@ -56,7 +56,7 @@ proc set_sysclk_500khz {} {
echo "Notice: sysclock set to 500kHz."
}
# Do not remap the ARM interrupt vectors to anything but the beginning ot the flash.
# Do not remap the ARM interrupt vectors to anything but the beginning of the flash.
# Table System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description
# Bit Symbol Value Description
# 0 map - interrupt vector remap. 0 after boot.
tcl/target/psoc4.cfg
+1 -1
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@@ -60,7 +60,7 @@ adapter speed 1500
#
# Newer families like PSoC 4000, 4100M, 4200M, 4100L, 4200L and PSoC 4 BLE
# clear TEST_MODE flag during device reset so workaround is not possible.
# Use a KitProg adapter for theese devices or "reset halt" will not stop
# Use a KitProg adapter for these devices or "reset halt" will not stop
# before executing user code.
#
# 3) SWD cannot be connected during system initialization after reset.