From upstream (#286)
* flash/nor: Add support for TI CC26xx/CC13xx flash Added cc26xx flash driver to support the TI CC26xx and CC13xx microcontrollers. Driver is capable of determining which MCU is connected and configures itself accordingly. Added config files for four specific variants: CC26x0, CC13x0, CC26x2, and CC13x2. Note that the flash loader code is based on the sources used to support flash in Code Composer Studio and Uniflash from TI. Removed cc26xx.cfg file made obsolete by this patch. Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4358 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> * flash/nor/nrf5: remove is_erased setting and autoerase before write Cached flash erase state in sectors[].is_erased is not reliable as running target can change the flash. Autoerase was issued before flash write on condition is_erased != 1 Remove autoerase completely as it is a quite non-standard feature. Change-Id: I19bef459e6afdc4c5fcaa2ccd194cf05be8a42b6 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4400 Tested-by: jenkins * src/flash/tms470: remove testing of sectors[].is_erased state The erase check routine checked sectors only if is_erased != 1 Check sector unconditionally. While on it fix clang static analyzer warnings. Change-Id: I9988615fd8530c55a9b0c54b1900f89b550345e9 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4401 Tested-by: jenkins * tcl/target/stm32f7x: configure faster system clock in reset-init STM32F7xx devices need faster clock for flash programming over JTAG transport. Using reset default 16 MHz clock resulted in lot of DAP WAITs and substantial decrease of flashing performance. Adapted to the restructured dap support (see2231da8ec4). Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4464 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> * flash/nor/psoc5lp: fix compile issue on GCC 8.1.0 Issue already identified by Alex https://sourceforge.net/u/alexbour/ in ticket #191 https://sourceforge.net/p/openocd/tickets/191/ src/flash/nor/psoc5lp.c:237:2: error: ‘strncpy’ output truncated before terminating nul copying 2 bytes from a string of the same length [-Werror=stringop-truncation] Fix it by assigning the value to the array elements. Change-Id: I22468e5700efa64ea48ae8cdec930c48b4a7d8fb Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4563 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/arm: Add PLD command to ARM disassembler. Updates the ARM disassembler to handle PLD (PreLoad Data) commands. Previously handled by printing a TODO message. There are three forms of the command: literal, register, and immediate. Simply decode based off of the A1 encoding for the instructions in the ARM ARM. Also fixes mask to handle PLDW commands. Change-Id: I63bf97f16af254e838462c7cfac80f6c4681c556 Signed-off-by: James Marshall <jcmarsh@gwmail.gwu.edu> Reviewed-on: http://openocd.zylin.com/4348 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> * mips_m4k.c: Fix build with --disable-target64 Replace PRIx64 with TARGET_PRIxADDR to avoid build problems when --disable-target64 is used during configure. Change-Id: I054a27a491e86c42c9386a0488194320b808ba96 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4566 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Tim Newsome <tim@sifive.com> * target/arm_adi_v5: sync CSW and TAR cache on apreg write When using apreg to change AP registers CSW or TAR we get internal cached value not valid anymore. Reuse the setup functions for CSW and TAR to write them. Invalidate the cached value before the call to force the write, thus keeping original apreg behaviour. Change-Id: Ib14fafd5e584345de94f2e983de55406c588ac1c Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4565 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/arm_adi_v5: keep CSW and TAR cache updated The call to dap_queue_ap_write() can fail and the value in CSW and TAR becomes unknown. Invalidate the OpenOCD cache if dap_queue_ap_write() fails. Change-Id: Id6ec370b4c5ad07e454464780c1a1c8ae34ac870 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4564 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * tcl/target: Add Renesas R-Car R8A7794 E2 target Add configuration for the Renesas R-Car R8A7794 E2 target. This is an SoC with two Cortex A7 ARMv7a cores, both A7 cores are supported. Change-Id: Ic1c81840e3bfcef8ee1de5acedffae5c83612a5e Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4531 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl/board: Add Renesas R-Car R8A7790 H2 Stout board Add configuration for the Renesas R-Car R8A7790 H2 based Stout ADAS board. Change-Id: Ib880b5d2e1fab5c8c0bc0dbcedcdce8055463fe2 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4497 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl/board: Add Renesas R-Car R8A7791 M2W Porter board Add configuration for the Renesas R-Car R8A7791 M2W based Porter evaluation board. Change-Id: Iaadb18f29748f890ebb68519ea9ddbd18e7649af Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4498 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl/board: Add Renesas R-Car R8A7794 E2 Silk board Add configuration for the Renesas R-Car R8A7794 E2 based Silk evaluation board. Change-Id: I504b5630b1a2791ed6967c6c2af8851ceef9723f Signed-off-by: Marek Vasut <marek.vasut@gmail.com> --- NOTE: This requires SW7[1] in position 1 (default is 0) Reviewed-on: http://openocd.zylin.com/4532 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl/board: Factor out common R-Car Gen2 code Factor out the code shared by all R-Car Gen2 boards into a single file to get rid of the duplication. Change-Id: I70b302c2e71f4e6fdccb2817dd65a5493bb393d8 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4533 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * jtag/drivers/cmsis-dap: fix connect in cmsis_dap_swd_switch_seq() The proc cmsis_dap_swd_switch_seq() is part of the SWD API for this interface driver. It is valid only when the interface is used in SWD mode. In this proc there is the need to call, in sequence, first cmsis_dap_cmd_DAP_Disconnect() then cmsis_dap_cmd_DAP_Connect(). The latter call requires the connection mode as parameter, that inside cmsis_dap_swd_switch_seq() can only be CONNECT_SWD. The current implementation is not correct and in some cases can pass mode CONNECT_JTAG. Moreover, JTAG is optional in CMSIS-DAP and passing mode CONNECT_JTAG triggers an error with SWD-only interfaces. Use mode CONNECT_SWD in SWD specific cmsis_dap_swd_switch_seq(). Change-Id: Ib455bf5b69cb2a2d146a6c8875387b00c27a5690 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4571 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/cortex_m: return error if breakpoint address is out of range If the "Flash Patch and Breakpoint" unit is rev.1 then it can only accept breakpoint addresses below 0x1FFFFFFF. Detailed info in "ARM v7-M Architecture Reference Manual", DDI0403E at chapter "C1.11 Flash Patch and Breakpoint unit". Print a message and return error if the address of hardware breakpoint cannot be handled by the breakpoint unit. Change-Id: I95c92b1f058f0dfc568bf03015f99e439b27c59b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4535 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com> * flash/nor/stm32: Report errors in wait_status_busy Flash operation errors that occur during algorithm programming are reported via the algorithm return value. However, Flash operation errors that occur during non-algorithm work (erasing, programming without a work area, programming the last non-multiple-of-32-bytes on an H7, etc.) generally end with a call to stm32x_wait_status_busy, which reads the status register and clears the error flags but fails to actually report that something went wrong should an error flag (other than WRPERR) be set. Return an error status from stm32x_wait_status_busy in those cases. Correct a log message accordingly. Change-Id: I09369ea5f924fe58833aec1f45e52320ab4aaf43 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4519 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * flash/nor/stm32: Eliminate working area leak On a specific early-return path, an allocated working area was not freed. Free it. Change-Id: I7c8fe51ff475f191624086996be1c77251780b77 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4520 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * flash/nor/stm32h7: Fix incorrect comment The name of the bit according to the reference manual is inconsistency error, not increment error. Change-Id: Ie3b73c0312db586e35519e03fd1a5cb225673d97 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4521 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> * target: fix 'bp' command help message "asid" and "length" are separate arguments of the command. Put space between them. Change-Id: I36cfc1e3a01caafef4fc3b26972a0cc192b0b963 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4511 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * Add ARM v8 AArch64 semihosting support This patch implements semihosting support for AArch64. This picks code from previously submitted AArch64 semihosting support patch and rebases on top of reworked semihosting code. Tested in AArch64 mode on a Lemaker Hikey Board with NewLib and GDB. Change-Id: I228a38f1de24f79e49ba99d8514d822a28c2950b Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4537 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * GDB fileIO stdout support This patch fixes gdb fileio support to allow gdb console to be used as stdout. Now we can do something like gdb <inferior file> (gdb) tar ext :3333 (gdb) load (gdb) monitor arm semihosting enable (gdb) monitor arm semihosting_fileio enable (gdb) continue Here: Output from inferior using puts, printf etc will be routed to gdb console. Change-Id: I9cb0dddda1de58038c84f5b035c38229828cd744 Signed-off-by: Omair Javaid <omair.javaid@linaro.org> Reviewed-on: http://openocd.zylin.com/4538 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * target: armv8: Avoid semihosting segfault on halt Avoid a NULL pointer dereference when halting an aarch64 core. Change-Id: I333d40475ab26e2f0dca5c27302a5fa4d817a12f Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/4593 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl: target: Add NXP LS1012A config As seen on the FRDM-LS1012A board. Change-Id: Ifc9074b3f7535167b9ded5f544501ec2879f5db7 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/4594 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl: board: Add NXP Freedom FRDM-LS1012A config An update for the K20 CMSIS-DAP firmware can be found here: https://community.nxp.com/thread/387080?commentID=840141#comment-840141 Change-Id: I149d7f8610aa56daf1aeb95f14ee1bf88f7cb647 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/4595 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * gdb_server: only trigger once the event gdb-detach at gdb quit When GDB quits (e.g. with "quit" command) we first execute gdb_detach() to reply "OK" then, at GDB disconnect (either TCP or pipe connection type), we execute gdb_connection_closed(). In case GDB is killed or it crashes, OpenOCD only executes the latter when detects the disconnection. Both gdb_detach() and gdb_connection_closed() trigger the event TARGET_EVENT_GDB_DETACH thus getting it triggered twice on clean GDB quit. Do not trigger the event TARGET_EVENT_GDB_DETACH in gdb_detach() and let only gdb_connection_closed() to handle it. Change-Id: Iacf035c855b8b3e2239c1c0e259c279688b418ee Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4585 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * gdb_server: set current_target from connection's one In a multi-target environment we are supposed to have a single gdb server for each target (or for each group of targets within a SMP node). By default, the gdb attached to a server sends its command to the target (or to the SMP node targets) linked to that server. This is working fine for the normal gdb commands, but it is broken for the native OpenOCD commands executed through gdb "monitor" command. In the latter case, gdb "monitor" commands will be executed on the current target of OpenOCD configuration script (that is either the last target created or the target specified in a "targets" command). Fixed in gdb_new_connection() by replacing the current target in the connection's copy of command context. Change-Id: If7c8f2dce4a3138f0907d3000dd0b15e670cfa80 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4586 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com> * target/image: make i/j unsigned to avoid ubsan runtime error src/target/image.c:1055:15: runtime error: left shift of 128 by 24 places cannot be represented in type 'int' Change-Id: I322fd391cf3f242beffc8a274824763c8c5e69a4 Signed-off-by: Cody Schafer <openocd@codyps.com> Reviewed-on: http://openocd.zylin.com/4584 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com> * target/stm32f7x: Clear stuck HSE clock with CSS Change-Id: Ica0025ea465910dd664ab546b66f4f25b271f1f5 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4570 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> * psoc5lp: fix erase check, add free_driver_priv psoc5lp_erase_check() was not properly adapted to the new armv7m_blank_check_memory() in the hot fix53376dbbedThis change fixes handling of num_sectors in dependecy of ecc_enabled. Also add comments how ecc_enabled influences num_sectors. Add pointer to default_flash_free_driver_priv() to all psoc5lp flash drivers to keep valgrind happy. Change-Id: Ie1806538becd364fe0efb7a414f0fe6a84b2055b Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4569 Tested-by: jenkins * target: atmel samd10 xplained mini cortex m0+ on a tiny board, with an mEDBG (CMSIS-DAP) debug interface. Change-Id: Iaedfab578b4eb4aa2d923bd80f220f59b34e6ef9 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/3402 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * tcl/board: add SAMD11 Xplained Pro evaluation board Change-Id: Id996c4de6dc9f25f71424017bf07689fea7bd3af Signed-off-by: Peter Lawrence <majbthrd@gmail.com> Reviewed-on: http://openocd.zylin.com/4507 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * Adds SAMD11D14AU flash support. Corrects names of SAMD11D14AM and SAMD11D14ASS per datasheet. Change-Id: I8beb15d5376966a4f8d7de76bfb2cbda2db440dc Signed-off-by: Christopher Hoover <ch@murgatroid.com> Reviewed-on: http://openocd.zylin.com/4597 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * nds32: Avoid detected JTAG clock AICE2 doesn't support scan for the maximum clock frequency of JTAG chain. It will cause USB command timeout. Change-Id: I41d1e3be387b6ed5a4dd0be663385a5f053fbcf9 Signed-off-by: Hellosun Wu <wujiheng.tw@gmail.com> Reviewed-on: http://openocd.zylin.com/4292 Tested-by: jenkins Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * flash/nor/tcl: Distinguish between sectors and blocks in status messages Use the right word in flash protect command status messages based on whether the target bank defines num_prot_blocks. Minor message style tidy-up. Change-Id: I5f40fb5627422536ce737f242fbf80feafe7a1fc Signed-off-by: Dominik Peklo <dom.peklo@gmail.com> Reviewed-on: http://openocd.zylin.com/4573 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Christopher Head <chead@zaber.com> * drivers: cmsis-dap: pull up common connect code Just a minor deduplication Change-Id: Idd256883e5f6d4bd4dcc18462dd5468991f507b3 Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/3403 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * drivers: cmsis-dap: Print version info when available No need to wait until after connecting, might help diagnose part information by printing earlier. Change-Id: I51eb0d584be306baa811fbeb1ad6a604773e602c Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/3404 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * flash/nor: add support for TI MSP432 devices Added msp432 flash driver to support the TI MSP432P4x and MSP432E4x microcontrollers. Implemented the flash algo helper as used in the TI debug and flash tools. This implemention supports the MSP432E4, Falcon, and Falcon 2M variants. The flash driver automatically detects the connected variant and configures itself appropriately. Added command to mass erase device for consistency with TI tools and added command to unlock the protected BSL region. Tested using MSP432E401Y, MSP432P401R, and MSP432P4111 LaunchPads. Tested with embedded XDS110 debug probe in CMSIS-DAP mode and with external SEGGER J-Link probe. Removed ti_msp432p4xx.cfg file made obsolete by this patch. Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4153 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * flash/nor/at91sam4: fix sam4sa16c flash banks and its gpnvms count There was already a github fork that had this fixed, but as we try to use the latest, non-modified version of all software we use, I would like to have this fix in the next releases of OpenOCD so that if people uses $packagemanager, they will not have issues flashing the last part of the flash of sam4sa16c chips. Additionally, I've added some more logging related to the flash bank that was used, and the chip ID that was detected. Change-Id: I7ea5970105906e4560b727e46222ae9a91e41559 Signed-off-by: Erwin Oegema <blablaechthema@hotmail.com> Reviewed-on: http://openocd.zylin.com/4599 Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Tested-by: jenkins * flash/nor/stm32lx: Add revision 'V' for STM32L1xx Cat.3 devices Change-Id: Ic92b0fb5b738af3bec79ae335876aa9e26f5f4cd Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4600 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * Avoid null target->semihosting references. The new common semihosting code introduced a bug, in certain conditions target->semihosting was used without semihosting being initialised. The solution was to explicitly test for target->semihosting before dereferencing it. Change-Id: I4c83e596140c68fe4ab32e586e51f7e981a40798 Signed-off-by: Liviu Ionescu <ilg@livius.net> Reviewed-on: http://openocd.zylin.com/4603 Tested-by: jenkins Reviewed-by: Jonathan Larmour <jifl@eCosCentric.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * nrf5: Add HWID 0x139 (52832 rev E0) Change-Id: I71b7471ccfcb8fcc6de30da57ce4165c7fb1f73f Signed-off-by: James Jacobsson <slowcoder@gmail.com> Reviewed-on: http://openocd.zylin.com/4604 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target: Fix segfault for 'mem2array' Call 'mem2array' without arguments to reproduce the segmentation fault. Change-Id: I02bf46cc8bd317abbb721a8c75d7cbfac99eb34e Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4534 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Christopher Head <chead@zaber.com> * target/armv7m_trace: Fix typo in enum Change-Id: I6364ee5011ef2d55c59674e3b97504a285de0cb2 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3904 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * target/armv7m_trace: Use prefix for enums Change-Id: I3f199e6053146a1094d96b98ea174b41bb021599 Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3905 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * target/aarch64: Call aarch64_init_debug_access() earlier in aarch64_deassert_reset() On Renesas R-Car, calling 'reset halt' and 'reset init' always made DAP inaccessible. Calling 'reset' and 'halt' seperatly worked fine. The only differences seems to be the point in time when aarch64_init_debug_access() is called. This patch aligns the behaviour. Change-Id: I2296c65e48414a7d9846f12a395e5eca315b49ca Signed-off-by: Dennis Ostermann <dennis.ostermann@renesas.com> Reviewed-on: http://openocd.zylin.com/4607 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * server: Improve signal handling under Linux Commit5087a955added custom signal handlers for the openocd server process. Before this commit, when openocd is run as a background process having the same controlling terminal as gdb, Control-C would be handled by gdb to stop target execution and return to the gdb prompt. However, after commit5087a955, the SIGINT caused by pressing Control-C also terminates openocd, effectively crashing the debugging session. The only way to avoid this is run openocd in a different controling terminal or to detach openocd from its controlling terminal, thus losing all job control for the openocd process. This patch improves the server's handling of POSIX signals: 1) Keyboard generated signals (INT and QUIT) are ignored when server process has is no controlling terminal. 2) SIGHUP and SIGPIPE are handled to ensure that .quit functions for each interface are called if user's logs out of X session or there is a network failure. SIG_INT & SIG_QUIT still stop openocd when it is running in the foreground. Change-Id: I03ad645e62408fdaf4edc49a3550b89b287eda10 Signed-off-by: Brent Roman <genosensor@gmail.com> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3963 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> * armv7a: read ttbcr and ttb0/1 at every entry in debug state Commitbfc5c764dfavoids reading ttbcr and ttb0/1 at every virt2phys translation by caching them, and it updates the cached values in armv7a_arch_state(). But the purpose of any (*arch_state)() method, thus including armv7a_arch_state(), is to only print out and inform the user about some architecture specific status. Moreover, to reduce the verbosity during a GDB session, the method (*arch_state)() is not executed anymore at debug state entry (check use of target->verbose_halt_msg in src/openocd.c), thus the state of translation table gets out-of-sync triggering Error: Address translation failure or even using a wrong address in the memory R/W operation. In addition, the commit above breaks the case of armv7r by calling armv7a_read_ttbcr() unconditionally. Fixed by moving in cortex_a_post_debug_entry() the call to armv7a_read_ttbcr() on armv7a case only. Remove the call to armv7a_read_ttbcr() in armv7a_identify_cache() since it is (conditionally) called only in the same procedure cortex_a_post_debug_entry(). Fixes:bfc5c764df("armv7a: cache ttbcr and ttb0/1 on debug state entry") Change-Id: Ifc20eca190111832e339a01b7f85d28c1547c8ba Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4601 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * Avoid dereferencing NULL pointer. If a NULL pointer is passed, don't attempt to increment it. This avoids passing the now not-NULL pointer on and eventually segfaulting. Also remove some unnecessary temporary variables. Change-Id: I268e225121aa283d59179bfae407ebf6959d3a4e Signed-off-by: Darius Rad <darius@bluespec.com> Reviewed-on: http://openocd.zylin.com/4550 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> * Remove FSF mailing address. Checkpatch complains about this (FSF_MAILING_ADDRESS). Change-Id: Ib46a7704f9aed4ed16ce7733d43c58254a094149 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4559 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> * drivers: cmsis_dap_usb: implement cmd JTAG_TMS Simply add a wrapper around cmsis_dap_cmd_DAP_SWJ_Sequence() Change-Id: Icf86f84b24e9fec56e2f9e155396aac34b0e06d2 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4517 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk> * arm_adi_v5: put SWJ-DP back to JTAG mode at exit When SWD mode is used, current OpenOCD code left the SWJ-DP in SWD mode at exit. Also, current code is unable to switch back the SWJ-DP in JTAG at next run, thus a power cycle of both target and interface is required in order to run OpenOCD in JTAG mode again. Put the SWJ-DP back to JTAG mode before exit from OpenOCD. Use switch_seq(SWD_TO_JTAG) instead of dap_to_jtag(), because the latter is not implemented on some interfaces. This is aligned with the use of switch_seq(JTAG_TO_SWD) in swd_connect(). Change-Id: I55d3faebe60d6402037ec39dd9700dc5f17c53b0 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4493 Tested-by: jenkins Reviewed-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * Add RISC-V support. This supports both 0.11 and 0.13 versions of the debug spec. Support for `-rtos riscv` will come in a separate commit since it was easy to separate out, and is likely to be more controversial. Flash support for the SiFive boards will also come in a later commit. Change-Id: I1d38fe669c2041b4e21a5c54a091594aac3e2190 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: http://openocd.zylin.com/4578 Tested-by: jenkins Reviewed-by: Liviu Ionescu <ilg@livius.net> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * usb_blaster: Don't unnecessarily go through DR-/IR-Pause There is no need to pass through DR-/IR-Pause after a scan if we want to go to DR-/IR-Update. We just have to skip the first step of the path to the end state because we already did that step when shifting the last bit. v2: - Fix comments as remarked in review of v1 Change-Id: I3c10f02794b2233f63d2150934e2768430873caa Signed-off-by: Daniel Glöckner <daniel-gl@gmx.net> Reviewed-on: http://openocd.zylin.com/4245 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * cortex_a: fix virt2phys when mmu is disabled When the MMU is not enabled on debug state entry, virt2phys cannot perform a translation since it is unknown whether a valid MMU configuration existed before. In this case, return the virtual address as physical address. Change-Id: I6f85a7a5dbc200be1a4b5badf10a1a717f1c79c0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4480 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * drivers: cmsis-dap: print serial if available Helpful for sanity checking connections Change-Id: Ife0d8b4e12d4c03685aac8115c9739a4c1e994fe Signed-off-by: Karl Palsson <karlp@tweak.net.au> Reviewed-on: http://openocd.zylin.com/3405 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/cortex_m: make a variable local The vec_ids variable is not referenced anywhere other than the vector catch command handler. Make it local to that function. Change-Id: Ie5865e8f78698c19a09f0b9d58269ced1c9db440 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4606 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/cortex_a: fix compile error for uninitialized variable Commitad6c71e151introduced the variable "mmu_enabled" whose pointer is passed to cortex_a_mmu() that initialises it. This initialization is not visible to the compiler that issue a compile error. The same situation is common across the same file and the usual workaround is to initialize it to zero; thus the same fix i applied here. Ticket: https://sourceforge.net/p/openocd/tickets/197/ Fixes: commitad6c71e151("cortex_a: fix virt2phys when mmu is disabled") Change-Id: I77dec41acdf4c715b45ae37b72e36719d96d9283 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4619 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * mips_m4k: add optional reset handler In some cases by using SRST we can't halt CPU early enough. And option PrRst is not available too. In this case the only way is to set BOOT flag over EJTAG and reset CPU or SoC from CPU itself. For example by writing to some reset register. This patch is providing possibility to use user defined reset-assert handler which will be enabled only in case SRST is disabled. It is needed to be able switch between two different reset variants on run time. Change-Id: I6ef98f1871ea657115877190f7cc7a5e8f3233e4 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4404 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * tcl/target: add config for Qualcomm QCA4531 The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT). https://www.qualcomm.com/products/qca4531 Change-Id: I58398c00943b005cfaf0ac1eaad92d1fa4e2cba7 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4405 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * tcl/board: add config for 8devices LIMA board More information about this board can be found here: https://www.8devices.com/products/lima Change-Id: Id35a35d3e986630d58d37b47828870afd107cc6a Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4406 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * tcl/target|board: move common AR9331 code to atheros_ar9331.cfg The ar9331_25mhz_pll_init and ar9331_ddr1_init routines can be used not only for TP-Link MR3020 board, so move them to the common atheros_ar9331.cfg file. Change-Id: I04090856b08151d6bb0f5ef9cc654efae1c81835 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2999 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * tcl/target/atheros_ar9331: add DDR2 helper this helper works on many different boards, so it is good to have it in target config Change-Id: I068deac36fdd73dbbcedffc87865cc5b9d992c1d Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4422 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * tcl/target/atheros_ar9331: add documentation and extra helpers Sync it with experience gathered on Qualcomm QCA4531 SoC. This chips are in many ways similar. Change-Id: I06b9c85e5985a09a9be3cb6cc0ce3b37695d2e54 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4423 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * tcl/board: add DPTechnics DPT-Board-v1 it is Atheros AR9331 based IoT dev board. Change-Id: I6fc3cdea1bef49c53045018ff5acfec4d5610ba6 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4424 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * fpga/altera-10m50: add all device id add all currently know Intel (Alter) MAX 10 device ids Change-Id: I6a88fef222c8e206812499d41be863c3d89fa944 Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-on: http://openocd.zylin.com/4598 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * target|board: Add Intel (Altera) Arria 10 target and related board Target information about this SoC can be found here: https://www.altera.com/products/fpga/arria-series/arria-10/overview.html Achilles Instant-Development Kit Arria 10 SoC SoM: https://www.reflexces.com/products-solutions/development-kits/arria-10/achilles-instant-development-kit-arria-10-soc-som Change-Id: Id78c741be6a8b7d3a70f37d41088e47ee61b437a Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-on: http://openocd.zylin.com/4583 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * target/riscv: fix compile error with gcc 8.1.1 Fix compile error: src/target/riscv/riscv-011.c: In function ‘slot_offset’: src/target/riscv/riscv-011.c:238:4: error: this statement may fall through [-Werror=implicit-fallthrough=] switch (slot) { ^~~~~~ src/target/riscv/riscv-011.c:243:3: note: here case 64: ^~~~ Fixes:a51ab8ddf6("Add RISC-V support.") Change-Id: I7fa86b305bd90cc590fd4359c3698632d44712e5 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4618 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-by: Tim Newsome <tim@sifive.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> * server: explicitly call "shutdown" when catch CTRL-C or a signal Every TCL command can be renamed (or deleted) and then replaced by a TCL proc that has the same name of the original TCL command. This can be used either to completely replace an existing command or to wrap the original command to extend its functionality. This applies also to the OpenOCD command "shutdown" and can be useful, for example, to set back some default value to the target before quitting OpenOCD. E.g. (TCL code): rename shutdown original_shutdown proc shutdown {} { puts "This is my implementation of shutdown" # my own stuff before exit OpenOCD original_shutdown } Unfortunately, sending a signal (or pressing CTRL-C) to terminate OpenOCD doesn't trigger calling the original "shutdown" command nor its (eventual) replacement. Detect if the main loop is terminated by an external signal and in such case execute explicitly the command "shutdown". Replace with enum the magic numbers assumed by "shutdown_openocd". Please notice that it's possible to write a custom "shutdown" TCL proc that does not call the original "shutdown" command. This is useful, for example, to prevent the user to quit OpenOCD by typing "shutdown" in the telnet session. Such case will not prevent OpenOCD to terminate when receiving a signal; OpenOCD will quit after executing the custom "shutdown" command. Change-Id: I86b8f9eab8dbd7a28dad58b8cafd97caa7a82f43 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4551 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * zy1000: fix compile error with gcc 8.1.1 The fall-through comment is not taken in consideration by gcc 8.1.1 because it is inside the braces of a C-code block. Move the comment outside the C block. Change-Id: I22d87b2dee109fb8bcf2071ac55fdf7171ffcf4b Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4614 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * flash/nor/tcl.c: fix flash bank bounds check in 'flash fill' command handler Steps to reproduce ( STM32F103 'Blue Pill', 128KiB of flash ): > flash fillh 0x0801FFFE 00 1 wrote 2 bytes to 0x0801fffe in 0.019088s (0.102 KiB/s) > flash fillw 0x0801FFFE 00 1 Error: stm32f1x.cpu -- clearing lockup after double fault Error: error waiting for target flash write algorithm Error: error writing to flash at address 0x08000000 at offset 0x0001fffe Change-Id: I145092ec5e45bc586b3df48bf37c38c9226915c1 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4516 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/arm_adi_v5: add command "dpreg" For very low level debug or development around DAP, it is useful to have direct access to DP registers. Add command "dpreg" by mimic the syntax of the existing "apreg" command: $dap_name dpreg reg [value] Change-Id: Ic4ab451eb5e74453133adee61050b4c6f656ffa3 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4612 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * nrf5: add free_driver_priv Change-Id: I429a9868deb0c4b51f47a4bbad844bdc348e8d21 Signed-off-by: Jim Paris <jim@jtan.com> Reviewed-on: http://openocd.zylin.com/4608 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * rtos: add support for NuttX This patch introduces RTOS support for NuttX. Currently, only ARM Cortex-M (both FPU and FPU-less) targets are supported. To use, add the following lines to ~/.gdbinit. define hookpost-file eval "monitor nuttx.pid_offset %d", &((struct tcb_s *)(0))->pid eval "monitor nuttx.xcpreg_offset %d", &((struct tcb_s *)(0))->xcp.regs eval "monitor nuttx.state_offset %d", &((struct tcb_s *)(0))->task_state eval "monitor nuttx.name_offset %d", &((struct tcb_s *)(0))->name eval "monitor nuttx.name_size %d", sizeof(((struct tcb_s *)(0))->name) end And please make sure the above values are the same as in src/rtos/nuttx_header.h Change-Id: I2aaf8644d24dfb84b500516a9685382d5d8fe48f Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com> Signed-off-by: Masatoshi Tateishi <Masatoshi.Tateishi@jp.sony.com> Signed-off-by: Nobuto Kobayashi <Nobuto.Kobayashi@sony.com> Reviewed-on: http://openocd.zylin.com/4103 Tested-by: jenkins Reviewed-by: Alan Carvalho de Assis <acassis@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * server/server: Add ability to remove services Add the ability to remove services while OpenOCD is running. Change-Id: I4067916fda6d03485463fa40901b40484d94e24e Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/4054 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/cortex_m: fix incorrect comment The code sets C_MASKINTS if that bit is not already set (correctly). Fix the comment to agree. Change-Id: If4543e2660a9fa2cdabb2d2698427a6c8d9a274c Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4620 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * tcl/target/stm32f0x: Allow overriding the Flash bank size Copy & paste from another stm32 target. Change-Id: I0f6cbcec974ce70c23c1850526354106caee1172 Signed-off-by: Dominik Peklo <dom.peklo@gmail.com> Reviewed-on: http://openocd.zylin.com/4575 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * tcl/target: add Allwinner V3s SoC support Change-Id: I2459d2b137050985b7301047f9651951d72d9e9e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4427 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com> * target/arm_adi_v5: allow commands apsel and apcsw during init phase The current implementation of apsel cannot be executed during the initialization phase because it queries the DAP AP to retrieve and print the content of IDR register, and the query is only possible later on during the exec phase. But IDR information is already printed by the dedicated command apid, making redundant printing it by apsel too. Being unable to run apsel during initialization, makes also apcsw command (that depends on apsel) not usable in such phase. Modify the command apsel to only set the current AP, without making any transfer to the (possibly not initialized yet) DAP. When run without parameters, just print the current AP number. Change mode to COMMAND_ANY to apsel and to apcsw. Change-Id: Ibea6d531e435d1d49d782de1ed8ee6846e91bfdf Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4624 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/cortex_a: allow command dacrfixup during init phase There is no reason to restrict the command "cortex_a dacrfixup" to the EXEC phase only. Change the command mode to ANY so the command can be used in the initialization phase too. Change-Id: I498cc6b2dbdc48b3b2dd5f0445519a51857b295f Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4623 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * target/armv7a_cache: add gdb keep-alive and fix a missing dpm finish Depending on range size, the loop on cache operations can take quite some time, causing gdb to timeout. Add keep-alive to prevent gdb to timeout. Add also a missing dpm->finish() to balance dpm->prepare(). Change-Id: Ia87934b1ec19a0332bb50e3010b582381e5f3685 Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-on: http://openocd.zylin.com/4627 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> * Add detail to `wrong register size` error. Signed-off-by: Tim Newsome <tim@sifive.com> Change-Id: Id31499c94b539969970251145e42c89c943fd87c Reviewed-on: http://openocd.zylin.com/4577 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * doc: fix typo in cortex_m maskisr command Change-Id: I37795c320ff7cbf6f2c7434e03b26dbaf6fc6db4 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4621 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/cortex_m: restore C_MASKINTS after reset The cortex_m maskisr user-facing setting is not changed across a target reset. However, the in-core C_MASKINTS bit was always cleared as part of reset processing, meaning that a cortex_m maskisr on setting would not be respected after a reset. Set C_MASKINTS based on the user-facing setting value rather than always clearing it after reset. Change-Id: I5aa5b9dfde04a0fb9c6816fa55b5ef1faf39f8de Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4605 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * tcl/board: update all uses of interface/stlink-v2-1 to interface/stlink Change-Id: I5e27e84d022f73101376e8b4a1bdc65f58fd348a Signed-off-by: Cody P Schafer <openocd@codyps.com> Reviewed-on: http://openocd.zylin.com/4456 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> * target/riscv/riscv-011: fix compile warning about uninitialized variable In MSYS2 MinGW 64-bit git clone git://git.code.sf.net/p/openocd/code openocd $ gcc --version gcc.exe (Rev1, Built by MSYS2 project) 8.2.0 ./bootstrap ./configure --prefix= $ cat config.status | grep CFLAGS CFLAGS='-g -O2' make bindir = "bin-x64" depbase=`echo src/target/riscv/riscv-011.lo | sed 's|[^/]*$|.deps/&|;s|\.lo$||'`;\ /bin/sh ./libtool --tag=CC --mode=compile gcc -DHAVE_CONFIG_H -I. -D__USE_MINGW_ANSI_STDIO -I./src -I./src -I./src/helper -DPKGDATADIR=\"/mingw64/share/openocd\" -DBINDIR=\"bin-x64\" -I./jimtcl -I./jimtcl -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/target/riscv/riscv-011.lo -MD -MP -MF $depbase.Tpo -c -o src/target/riscv/riscv-011.lo src/target/riscv/riscv-011.c &&\ mv -f $depbase.Tpo $depbase.Plo libtool: compile: gcc -DHAVE_CONFIG_H -I. -D__USE_MINGW_ANSI_STDIO -I./src -I./src -I./src/helper -DPKGDATADIR=\"/mingw64/share/openocd\" -DBINDIR=\"bin-x64\" -I./jimtcl -I./jimtcl -Wall -Wstrict-prototypes -Wformat-security -Wshadow -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -g -O2 -MT src/target/riscv/riscv-011.lo -MD -MP -MF src/target/riscv/.deps/riscv-011.Tpo -c src/target/riscv/riscv-011.c -o src/target/riscv/riscv-011.o src/target/riscv/riscv-011.c: In function 'poll_target': src/target/riscv/riscv-011.c:1799:6: error: 'reg' may be used uninitialized in this function [-Werror=maybe-uninitialized] reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ src/target/riscv/riscv-011.c:1686:17: note: 'reg' was declared here unsigned int reg; ^~~ cc1.exe: all warnings being treated as errors make[2]: *** [Makefile:3250: src/target/riscv/riscv-011.lo] Error 1 Change-Id: I6996dcb866fbace26817636f4bedba09510a087f Signed-off-by: Svetoslav Enchev <svetoslav.enchev@gmail.com> Reviewed-on: http://openocd.zylin.com/4635 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Tim Newsome <tim@sifive.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tim Newsome
@@ -0,0 +1,30 @@
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# Product page:
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# https://www.8devices.com/products/lima
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#
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# Location of JTAG pins:
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# J2 GPIO0 JTAG TCK
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# J2 GPIO1 JTAG TDI
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# J2 GPIO2 JTAG TDO
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# J2 GPIO3 JTAG TMS
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# J2 RST directly connected to RESET_L of the SoC and can be used as
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# JTAG SRST. Note: this pin will also reset the debug engine.
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# J1 +3,3V Can be use as JTAG Vref
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# J1 or J2 GND Can be used for JTAG GND
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#
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# This board is powered from mini USB connecter which is also used
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# as USB to UART converted based on FTDI FT230XQ chip
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source [find target/qualcomm_qca4531.cfg]
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proc board_init { } {
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qca4531_ddr2_550_550_init
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}
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$_TARGETNAME configure -event reset-init {
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board_init
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}
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set ram_boot_address 0xa0000000
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$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
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flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
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@@ -0,0 +1,10 @@
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#
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# Atmel SAMD10 Xplained mini evaluation kit.
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# http://www.atmel.com/tools/atsamd10-xmini.aspx
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source [find interface/cmsis-dap.cfg]
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# chip name
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set CHIPNAME at91samd10d14
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source [find target/at91samdXX.cfg]
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@@ -0,0 +1,10 @@
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#
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# Atmel SAMD11 Xplained Pro evaluation kit.
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#
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source [find interface/cmsis-dap.cfg]
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# chip name
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set CHIPNAME at91samd11d14
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source [find target/at91samdXX.cfg]
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@@ -0,0 +1,32 @@
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# Product page:
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# https://www.dptechnics.com/en/products/dpt-board-v1.html
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#
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# JTAG is a 5 pin array located close to main module in following order:
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# 1. JTAG TCK
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# 2. JTAG TDO
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# 3. JTAG TDI
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# 4. JTAG TMS
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# 5. GND The GND is located near letter G of word JTAG on board.
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#
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# Two RST pins are connected to:
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# 1. GND
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# 2. GPIO11 this pin is located near letter R of word RST.
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#
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# To enable EJTAG mode, GPIO11 (RST[1]) pin should be pulled up. For example
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# with 10K resistor connected to V3.3 pin.
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#
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# This board is powered from micro USB connector. No real reset pin or button, for
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# example RESET_L is available.
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source [find target/atheros_ar9331.cfg]
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$_TARGETNAME configure -event reset-init {
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ar9331_25mhz_pll_init
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sleep 1
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ar9331_ddr2_init
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}
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set ram_boot_address 0xa0000000
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$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
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flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
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@@ -0,0 +1,15 @@
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#
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# NXP FRDM-LS1012A (Freedom)
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#
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#
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# NXP Kinetis K20
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#
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source [find interface/cmsis-dap.cfg]
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transport select jtag
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# Also offers a 10-pin 0.05" CoreSight JTAG connector.
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source [find target/ls1012a.cfg]
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reset_config srst_only
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@@ -0,0 +1,13 @@
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# Achilles Instant-Development Kit Arria 10 SoC SoM
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# https://www.reflexces.com/products-solutions/achilles-instant-development-kit-arria-10-soc-som
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#
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if { [info exists USE_EXTERNAL_DEBUGGER] } {
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echo "Using external debugger"
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} else {
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source [find interface/altera-usb-blaster2.cfg]
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usb_blaster_device_desc "Arria10 IDK"
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}
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source [find fpga/altera-10m50.cfg]
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source [find target/altera_fpgasoc_arria10.cfg]
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@@ -0,0 +1,14 @@
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# Renesas R-Car Gen2 Evaluation Board common settings
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reset_config trst_and_srst srst_nogate
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proc init_reset {mode} {
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# Assert both resets: equivalent to a power-on reset
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jtag_reset 1 1
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# Deassert TRST to begin TAP communication
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jtag_reset 0 1
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# TAP should now be responsive, validate the scan-chain
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jtag arp_init
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}
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@@ -0,0 +1,4 @@
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# Renesas R-Car M2 Evaluation Board
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source [find target/renesas_r8a7791.cfg]
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source [find board/renesas_gen2_common.cfg]
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@@ -0,0 +1,4 @@
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# Renesas R-Car E2 Evaluation Board
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source [find target/renesas_r8a7794.cfg]
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source [find board/renesas_gen2_common.cfg]
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@@ -0,0 +1,4 @@
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# Renesas R-Car H2 Evaluation Board
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source [find target/renesas_r8a7790.cfg]
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source [find board/renesas_gen2_common.cfg]
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@@ -1,7 +1,7 @@
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# STMicroelectronics STM32F7 Nucleo development board
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# Known boards: NUCLEO-F746ZG and NUCLEO-F767ZI
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source [find interface/stlink-v2-1.cfg]
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source [find interface/stlink.cfg]
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transport select hla_swd
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@@ -1,7 +1,7 @@
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# This is an ST NUCLEO-H743ZI board with single STM32H743ZI chip.
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# http://www.st.com/en/evaluation-tools/nucleo-h743zi.html
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source [find interface/stlink-v2-1.cfg]
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source [find interface/stlink.cfg]
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transport select hla_swd
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@@ -1,6 +1,6 @@
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# This is an ST NUCLEO-L073RZ board with single STM32L073RZ chip.
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# http://www.st.com/en/evaluation-tools/nucleo-l073rz.html
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source [find interface/stlink-v2-1.cfg]
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source [find interface/stlink.cfg]
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transport select hla_swd
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@@ -4,7 +4,7 @@
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# This is an ST EVAL-H753XI board with single STM32H753XI chip.
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# http://www.st.com/en/evaluation-tools/stm32h753i-eval.html
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source [find interface/stlink-v2-1.cfg]
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source [find interface/stlink.cfg]
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transport select hla_swd
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@@ -0,0 +1,7 @@
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#
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# TI CC13x0 LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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transport select jtag
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adapter_khz 2500
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source [find target/ti_cc13x0.cfg]
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@@ -0,0 +1,7 @@
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#
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# TI CC13x2 LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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adapter_khz 2500
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transport select jtag
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source [find target/ti_cc13x2.cfg]
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@@ -0,0 +1,7 @@
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#
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# TI CC26x0 LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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adapter_khz 2500
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transport select jtag
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source [find target/ti_cc26x0.cfg]
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@@ -0,0 +1,7 @@
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#
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# TI CC26x2 LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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adapter_khz 2500
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transport select jtag
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source [find target/ti_cc26x2.cfg]
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@@ -0,0 +1,7 @@
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#
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# TI MSP432 LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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adapter_khz 2500
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transport select swd
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source [find target/ti_msp432.cfg]
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@@ -1,39 +1,5 @@
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source [find target/atheros_ar9331.cfg]
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proc ar9331_25mhz_pll_init {} {
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mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
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mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
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mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
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;# OUTDIV | REFDIV | DIV_INT
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mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
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;# (disabled?)
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mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
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mww 0xb8050008 0x00008000 ;# remove bypass;
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;# AHB_POST_DIV - ratio 2
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}
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proc ar9331_ddr1_init {} {
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mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
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mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb800000c 0x2 ;# Extended mode register value.
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;# default 0x2 - Reset to weak driver, DLL on
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mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
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mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
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mww 0xb8000008 0x33 ;# mode reg: remove some bit?
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mww 0xb8000010 0x1 ;# Forces an MRS update cycl
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mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
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mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
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;# DQ[7:0], DQS_0
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mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
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;# DQ[15:8], DQS_1.
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mww 0xb8000018 0xff ;# DDR read and capture bit mask.
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;# Each bit represents a cycle of valid data.
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}
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$_TARGETNAME configure -event reset-init {
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ar9331_25mhz_pll_init
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sleep 1
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@@ -1,6 +1,22 @@
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# Altera MAX10 10M50SAE144C8GES FPGA
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# see MAX 10 FPGA Device Architecture
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# Table 3-1: IDCODE Information for MAX 10 Devices
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# Version Part Number Manuf. ID LSB
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# 0000 0011 0001 1000 0101 000 0110 1110 1
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jtag newtap 10m50 tap -expected-id 0x031850dd -irlen 10
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# Intel MAX 10M02 0x31810dd
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# Intel MAX 10M04 0x318a0dd
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# Intel MAX 10M08 0x31820dd
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# Intel MAX 10M16 0x31830dd
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# Intel MAX 10M25 0x31840dd
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# Intel MAX 10M40 0x318d0dd
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# Intel MAX 10M50 0x31850dd
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# Intel MAX 10M02 0x31010dd
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# Intel MAX 10M04 0x310a0dd
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# Intel MAX 10M08 0x31020dd
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# Intel MAX 10M16 0x31030dd
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# Intel MAX 10M25 0x31040dd
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# Intel MAX 10M40 0x310d0dd
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# Intel MAX 10M50 0x31050dd
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jtag newtap 10m50 tap -irlen 10 -expected-id 0x31810dd -expected-id 0x318a0dd \
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-expected-id 0x31820dd -expected-id 0x31830dd -expected-id 0x31840dd \
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-expected-id 0x318d0dd -expected-id 0x31850dd -expected-id 0x31010dd \
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-expected-id 0x310a0dd -expected-id 0x31020dd -expected-id 0x31030dd \
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-expected-id 0x31040dd -expected-id 0x310d0dd -expected-id 0x31050dd
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@@ -0,0 +1,71 @@
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# This is the config for an Allwinner V3/V3s (sun8iw8).
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#
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# Notes:
|
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# - Single core ARM Cortex-A7 with a maximum frequency of 1.2 GHz.
|
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# - Thumb-2 Technology
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# - Support NEON Advanced SIMD(Single Instruction Multiple Data)instruction
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# for acceleration of media and signal processing functions
|
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# - Support Large Physical Address Extensions(LPAE)
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# - VFPv4 Floating Point Unit
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# - 32KB L1 Instruction cache and 32KB L1 Data cache
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# - 128KB L2 cache
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# - has some integrated DDR2 RAM.
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#
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# Pins related for debug and bootstrap:
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# JTAG
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# JTAG_TMS PF0, SDC0_D1
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# JTAG_TDI PF1, SDC0_D0
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# JTAG_TDO PF3, SDC0_CMD
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# JTAG_TCK PF5, SDC0_D2
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# UART
|
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# None of UART ports seems to be enabled by ROM.
|
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# UART0_TX PF2, SDC0_CLK Per default disabled
|
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# UART0_RX PF4, SDC0_D3 Per default disabled
|
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# UART1_TX PE21 Per default disabled
|
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# UART1_RX PE22 Per default disabled
|
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# UART2_TX PB0 Per default disabled
|
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# UART2_RX PB1 Per default disabled
|
||||
#
|
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# JTAG is enabled by default after power on on listed JTAG_* pins. So far the
|
||||
# boot sequence is:
|
||||
# Time Action
|
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# 0000ms Power ON
|
||||
# 0200ms JTAG enabled
|
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# 0220ms JTAG pins switched to SD mode
|
||||
#
|
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# The time frame of 20ms can be not enough to init and halt the CPU. In this
|
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# case I would recommend to set: "adapter_khz 15000"
|
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# To get more or less precise timings, the board should provide reset pin,
|
||||
# or some bench power supply with remote function. In my case I used
|
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# EEZ H24005 with this command to power on and halt the target:
|
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# "exec echo "*TRG" > /dev/ttyACM0; sleep 220; reset halt"
|
||||
# After this it is possible to enable JTAG mode again from boot loader or OS.
|
||||
# Following DAPs are available:
|
||||
# dap[0]->MEM-AP AHB
|
||||
# dap[1]->MEM-AP APB->CA7[0]
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME v3s
|
||||
}
|
||||
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x5ba00477
|
||||
}
|
||||
|
||||
# No NRST or SRST is present on the SoC. Boards may provide
|
||||
# some sort of Power cycle reset for complete board or SoC.
|
||||
# For this case we provide srst_pulls_trst so the board config
|
||||
# only needs to set srst_only.
|
||||
reset_config none srst_pulls_trst
|
||||
|
||||
jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x01 -irmask 0x0f \
|
||||
-expected-id $_DAP_TAPID
|
||||
|
||||
# Add Cortex A7 core
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap
|
||||
@@ -0,0 +1,56 @@
|
||||
# Intel (Altera) Arria10 FPGA SoC
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME arria10
|
||||
}
|
||||
|
||||
# ARM CoreSight Debug Access Port (dap HPS)
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x4ba00477
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_TAPID
|
||||
|
||||
# Subsidiary TAP: fpga (tap)
|
||||
# See Intel Arria 10 Handbook
|
||||
# https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/hb/arria-10/a10_handbook.pdf
|
||||
# Intel Arria 10 GX 160 0x02ee20dd
|
||||
# Intel Arria 10 GX 220 0x02e220dd
|
||||
# Intel Arria 10 GX 270 0x02ee30dd
|
||||
# Intel Arria 10 GX 320 0x02e230dd
|
||||
# Intel Arria 10 GX 480 0x02e240dd
|
||||
# Intel Arria 10 GX 570 0x02ee50dd
|
||||
# Intel Arria 10 GX 660 0x02e250dd
|
||||
# Intel Arria 10 GX 900 0x02ee60dd
|
||||
# Intel Arria 10 GX 1150 0x02e660dd
|
||||
# Intel Arria 10 GT 900 0x02e260dd
|
||||
# Intel Arria 10 GT 1150 0x02e060dd
|
||||
# Intel Arria 10 SX 160 0x02e620dd
|
||||
# Intel Arria 10 SX 220 0x02e020dd
|
||||
# Intel Arria 10 SX 270 0x02e630dd
|
||||
# Intel Arria 10 SX 320 0x02e030dd
|
||||
# Intel Arria 10 SX 480 0x02e040dd
|
||||
# Intel Arria 10 SX 570 0x02e650dd
|
||||
# Intel Arria 10 SX 660 0x02e050dd
|
||||
jtag newtap $_CHIPNAME.fpga tap -irlen 10 -expected-id 0x02ee20dd -expected-id 0x02e220dd \
|
||||
-expected-id 0x02ee30dd -expected-id 0x02e230dd -expected-id 0x02e240dd \
|
||||
-expected-id 0x02ee50dd -expected-id 0x02e250dd -expected-id 0x02ee60dd \
|
||||
-expected-id 0x02e660dd -expected-id 0x02e260dd -expected-id 0x02e060dd \
|
||||
-expected-id 0x02e620dd -expected-id 0x02e020dd -expected-id 0x02e630dd \
|
||||
-expected-id 0x02e030dd -expected-id 0x02e040dd -expected-id 0x02e650dd \
|
||||
-expected-id 0x02e050dd
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
|
||||
#
|
||||
# Cortex-A9 target
|
||||
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||
|
||||
target create $_TARGETNAME.0 cortex_a -dap $_CHIPNAME.dap -coreid 0
|
||||
target create $_TARGETNAME.1 cortex_a -dap $_CHIPNAME.dap -coreid 1 \
|
||||
-defer-examine
|
||||
target smp $_TARGETNAME.0 $_TARGETNAME.1
|
||||
@@ -1,16 +1,171 @@
|
||||
# The Atheros AR9331 is a highly integrated and cost effective
|
||||
# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
|
||||
# local area network (WLAN) AP and router platforms.
|
||||
#
|
||||
# Notes:
|
||||
# - MIPS Processor ID (PRId): 0x00019374
|
||||
# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
|
||||
# operating at up to 400 MHz
|
||||
# - External 16-bit DDR1, DDR2, or SDRAM memory interface
|
||||
# - TRST is not available.
|
||||
# - EJTAG PrRst signal is not supported
|
||||
# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
|
||||
#
|
||||
|
||||
# Pins related for debug and bootstrap:
|
||||
# Name Pin Description
|
||||
# JTAG
|
||||
# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
|
||||
# JTAG_TDI GPIO6, (B46) Software configurable, default JTAG
|
||||
# JTAG_TDO GPIO7, (A54) Software configurable, default JTAG
|
||||
# JTAG_TMS GPIO8, (A52) Software configurable, default JTAG
|
||||
# Reset
|
||||
# RESET_L -, (A72) Input only
|
||||
# SYS_RST_L ???????? Output reset request or GPIO
|
||||
# Bootstrap
|
||||
# MEM_TYPE[1] GPIO28, (A74) 0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
|
||||
# MEM_TYPE[0] GPIO12, (A56)
|
||||
# FW_DOWNLOAD GPIO16, (A75) Used if BOOT_FROM_SPI = 0. 0 - boot from USB
|
||||
# 1 - boot from MDIO.
|
||||
# JTAG_MODE(JS) GPIO11, (B48) 0 - JTAG (Default); 1 - EJTAG
|
||||
# BOOT_FROM_SPI GPIO1, (A77) 0 - ROM boot; 1 - SPI boot
|
||||
# SEL_25M_40M GPIO0, (A78) 0 - 25MHz; 1 - 40MHz
|
||||
# UART
|
||||
# UART0_SOUT GPIO10, (A79)
|
||||
# UART0_SIN GPIO9, (B68)
|
||||
|
||||
# Per default we need to use "none" variant to be able properly "reset init"
|
||||
# or "reset halt" the CPU.
|
||||
reset_config none srst_pulls_trst
|
||||
|
||||
# For SRST based variant we still need proper timings.
|
||||
# For ETH part the reset should be asserted at least for 10ms
|
||||
# Since there is no other information let's take 100ms to be sure.
|
||||
adapter_nsrst_assert_width 100
|
||||
|
||||
# according to the SoC documentation it should take at least 5ms from
|
||||
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
|
||||
# to live.
|
||||
adapter_nsrst_delay 8
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ar9331
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x00000001
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
|
||||
|
||||
# provide watchdog helper.
|
||||
proc disable_watchdog { } {
|
||||
mww 0xb8060008 0x0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event halted { disable_watchdog }
|
||||
|
||||
# Since PrRst is not supported and SRST will reset complete chip
|
||||
# with JTAG engine, we need to reset CPU from CPU itself.
|
||||
$_TARGETNAME configure -event reset-assert-pre {
|
||||
halt
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-assert {
|
||||
catch "mww 0xb806001C 0x01000000"
|
||||
}
|
||||
|
||||
# To be able to trigger complete chip reset, in case JTAG is blocked
|
||||
# or CPU not responding, we still can use this helper.
|
||||
proc full_reset { } {
|
||||
reset_config srst_only
|
||||
reset
|
||||
halt
|
||||
reset_config none
|
||||
}
|
||||
|
||||
proc disable_watchdog { } {
|
||||
;# disable watchdog
|
||||
mww 0xb8060008 0x0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-end { disable_watchdog }
|
||||
|
||||
# Section with helpers which can be used by boards
|
||||
proc ar9331_25mhz_pll_init {} {
|
||||
mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
|
||||
mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
|
||||
mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
|
||||
;# OUTDIV | REFDIV | DIV_INT
|
||||
mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
|
||||
;# (disabled?)
|
||||
mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
|
||||
mww 0xb8050008 0x00008000 ;# remove bypass;
|
||||
;# AHB_POST_DIV - ratio 2
|
||||
}
|
||||
|
||||
proc ar9331_ddr1_init {} {
|
||||
mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
|
||||
mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
|
||||
|
||||
mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
|
||||
mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
|
||||
mww 0xb8000010 0x1 ;# Forces an MRS update cycl
|
||||
mww 0xb800000c 0x2 ;# Extended mode register value.
|
||||
;# default 0x2 - Reset to weak driver, DLL on
|
||||
mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
|
||||
mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
|
||||
mww 0xb8000008 0x33 ;# mode reg: remove some bit?
|
||||
mww 0xb8000010 0x1 ;# Forces an MRS update cycl
|
||||
mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
|
||||
mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
|
||||
;# DQ[7:0], DQS_0
|
||||
mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
|
||||
;# DQ[15:8], DQS_1.
|
||||
mww 0xb8000018 0xff ;# DDR read and capture bit mask.
|
||||
;# Each bit represents a cycle of valid data.
|
||||
}
|
||||
|
||||
proc ar9331_ddr2_init {} {
|
||||
mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
|
||||
mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
|
||||
|
||||
mww 0xb800008c 0x00000a59
|
||||
mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle
|
||||
|
||||
mww 0xb8000090 0x00000000
|
||||
mww 0xb8000010 0x00000010 ;# EMR2S update cycle
|
||||
|
||||
mww 0xb8000094 0x00000000
|
||||
mww 0xb8000010 0x00000020 ;# EMR3S update cycle
|
||||
|
||||
mww 0xb800000c 0x00000000
|
||||
mww 0xb8000010 0x00000002 ;# EMRS update cycle
|
||||
|
||||
mww 0xb8000008 0x00000100
|
||||
mww 0xb8000010 0x00000001 ;# MRS update cycle
|
||||
|
||||
mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle
|
||||
|
||||
mww 0xb8000010 0x00000004
|
||||
mww 0xb8000010 0x00000004 ;# AUTO REFRESH cycle
|
||||
|
||||
mww 0xb8000008 0x00000a33
|
||||
mww 0xb8000010 0x00000001 ;# MRS update cycle
|
||||
|
||||
mww 0xb800000c 0x00000382
|
||||
mww 0xb8000010 0x00000002 ;# EMRS update cycle
|
||||
|
||||
mww 0xb800000c 0x00000402
|
||||
mww 0xb8000010 0x00000002 ;# EMRS update cycle
|
||||
|
||||
mww 0xb8000014 0x00004186 ;# DDR_REFRESH
|
||||
mww 0xb800001c 0x00000008 ;# DDR_TAP_CTRL0
|
||||
mww 0xb8000020 0x00000009 ;# DDR_TAP_CTRL1
|
||||
|
||||
;# DDR read and capture bit mask.
|
||||
;# Each bit represents a cycle of valid data.
|
||||
;# 0xff: use 16-bit DDR
|
||||
mww 0xb8000018 0x000000ff
|
||||
}
|
||||
|
||||
@@ -0,0 +1,35 @@
|
||||
#
|
||||
# NXP LS1012A
|
||||
#
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME ls1012a
|
||||
}
|
||||
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x5ba00477
|
||||
}
|
||||
|
||||
if { [info exists SAP_TAPID] } {
|
||||
set _SAP_TAPID $SAP_TAPID
|
||||
} else {
|
||||
set _SAP_TAPID 0x06b2001d
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
|
||||
jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
|
||||
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
|
||||
|
||||
cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x80420000
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -dbgbase 0x80410000 -cti $_CHIPNAME.cti
|
||||
|
||||
target smp $_TARGETNAME
|
||||
|
||||
adapter_khz 2000
|
||||
@@ -0,0 +1,154 @@
|
||||
# The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable
|
||||
# Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT).
|
||||
#
|
||||
# Product page:
|
||||
# https://www.qualcomm.com/products/qca4531
|
||||
#
|
||||
# Notes:
|
||||
# - MIPS Processor ID (PRId): 0x00019374
|
||||
# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
|
||||
# operating at up to 650 MHz
|
||||
# - External 16-bit DDR1, operating at up to 200 MHz, DDR2 operating at up
|
||||
# to 300 MHz
|
||||
# - TRST is not available.
|
||||
# - EJTAG PrRst signal is not supported
|
||||
# - RESET_L pin B56 on the SoC will reset internal JTAG logic.
|
||||
#
|
||||
# Pins related for debug and bootstrap:
|
||||
# Name Pin Description
|
||||
# JTAG
|
||||
# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
|
||||
# JTAG_TDI GPIO1, (B23) Software configurable, default JTAG
|
||||
# JTAG_TDO GPIO2, (A28) Software configurable, default JTAG
|
||||
# JTAG_TMS GPIO3, (A29) Software configurable, default JTAG
|
||||
# Reset
|
||||
# RESET_L -, (B56) Input only
|
||||
# SYS_RST_L GPIO17, (A79) Output reset request or GPIO
|
||||
# Bootstrap
|
||||
# JTAG_MODE GPIO16, (A78) 0 - JTAG (Default); 1 - EJTAG
|
||||
# DDR_SELECT GPIO10, (A57) 0 - DDR2; 1 - DDR1
|
||||
# UART
|
||||
# UART0_SOUT GPIO10, (A57)
|
||||
# UART0_SIN GPIO9, (B49)
|
||||
|
||||
# Per default we need to use "none" variant to be able properly "reset init"
|
||||
# or "reset halt" the CPU.
|
||||
reset_config none srst_pulls_trst
|
||||
|
||||
# For SRST based variant we still need proper timings.
|
||||
# For ETH part the reset should be asserted at least for 10ms
|
||||
# Since there is no other information let's take 100ms to be sure.
|
||||
adapter_nsrst_assert_width 100
|
||||
|
||||
# according to the SoC documentation it should take at least 5ms from
|
||||
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
|
||||
# to live.
|
||||
adapter_nsrst_delay 8
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $_CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME qca4531
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
|
||||
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
|
||||
|
||||
# provide watchdog helper.
|
||||
proc disable_watchdog { } {
|
||||
mww 0xb8060008 0x0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event halted { disable_watchdog }
|
||||
|
||||
# Since PrRst is not supported and SRST will reset complete chip
|
||||
# with JTAG engine, we need to reset CPU from CPU itself.
|
||||
$_TARGETNAME configure -event reset-assert-pre {
|
||||
halt
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-assert {
|
||||
catch "mww 0xb806001C 0x01000000"
|
||||
}
|
||||
|
||||
# To be able to trigger complete chip reset, in case JTAG is blocked
|
||||
# or CPU not responding, we still can use this helper.
|
||||
proc full_reset { } {
|
||||
reset_config srst_only
|
||||
reset
|
||||
halt
|
||||
reset_config none
|
||||
}
|
||||
|
||||
# Section with helpers which can be used by boards
|
||||
proc qca4531_ddr2_550_550_init {} {
|
||||
# Clear reset flags for different SoC components
|
||||
mww 0xb806001c 0xfeceffff
|
||||
mww 0xb806001c 0xeeceffff
|
||||
mww 0xb806001c 0xe6ceffff
|
||||
|
||||
# PMU configurations
|
||||
# Internal Switcher
|
||||
mww 0xb8116c40 0x633c8176
|
||||
# Increase the DDR voltage
|
||||
mww 0xb8116c44 0x10200000
|
||||
# XTAL Configurations
|
||||
mww 0xb81162c0 0x4b962100
|
||||
mww 0xb81162c4 0x480
|
||||
mww 0xb81162c8 0x04000144
|
||||
# Recommended PLL configurations
|
||||
mww 0xb81161c4 0x54086000
|
||||
mww 0xb8116244 0x54086000
|
||||
|
||||
# PLL init
|
||||
mww 0xb8050008 0x0131001c
|
||||
mww 0xb8050000 0x40001580
|
||||
mww 0xb8050004 0x40015800
|
||||
mww 0xb8050008 0x0131001c
|
||||
mww 0xb8050000 0x00001580
|
||||
mww 0xb8050004 0x00015800
|
||||
mww 0xb8050008 0x01310000
|
||||
mww 0xb8050044 0x781003ff
|
||||
mww 0xb8050048 0x003c103f
|
||||
|
||||
# DDR2 init
|
||||
mww 0xb8000108 0x401f0042
|
||||
mww 0xb80000b8 0x0000166d
|
||||
mww 0xb8000000 0xcfaaf33b
|
||||
mww 0xb800015c 0x0000000f
|
||||
mww 0xb8000004 0xa272efa8
|
||||
mww 0xb8000018 0x0000ffff
|
||||
mww 0xb80000c4 0x74444444
|
||||
mww 0xb80000c8 0x00000444
|
||||
mww 0xb8000004 0xa210ee28
|
||||
mww 0xb8000004 0xa2b2e1a8
|
||||
mww 0xb8000010 0x8
|
||||
mww 0xb80000bc 0x0
|
||||
mww 0xb8000010 0x10
|
||||
mww 0xb80000c0 0x0
|
||||
mww 0xb8000010 0x40
|
||||
mww 0xb800000c 0x2
|
||||
mww 0xb8000010 0x2
|
||||
mww 0xb8000008 0xb43
|
||||
mww 0xb8000010 0x1
|
||||
mww 0xb8000010 0x8
|
||||
mww 0xb8000010 0x4
|
||||
mww 0xb8000010 0x4
|
||||
mww 0xb8000008 0xa43
|
||||
mww 0xb8000010 0x1
|
||||
mww 0xb800000c 0x382
|
||||
mww 0xb8000010 0x2
|
||||
mww 0xb800000c 0x402
|
||||
mww 0xb8000010 0x2
|
||||
mww 0xb8000014 0x40be
|
||||
mww 0xb800001C 0x20
|
||||
mww 0xb8000020 0x20
|
||||
mww 0xb80000cc 0xfffff
|
||||
|
||||
# UART GPIO programming
|
||||
mww 0xb8040000 0xff30b
|
||||
mww 0xb8040044 0x908
|
||||
mww 0xb8040034 0x160000
|
||||
}
|
||||
@@ -0,0 +1,27 @@
|
||||
# Renesas R-Car E2
|
||||
# https://www.renesas.com/en-us/solutions/automotive/products/rcar-e2.html
|
||||
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x4ba00477
|
||||
}
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME r8a7794
|
||||
}
|
||||
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
|
||||
|
||||
# Configuring only one core using DAP.
|
||||
# Base addresses of cores:
|
||||
# core 0 - 0x800F0000
|
||||
# core 1 - 0x800F2000
|
||||
set _TARGETNAME $_CHIPNAME.ca7.
|
||||
dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
|
||||
target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800F0000
|
||||
target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800F2000 -defer-examine
|
||||
|
||||
targets ${_TARGETNAME}0
|
||||
@@ -22,6 +22,14 @@ if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE 0x1000
|
||||
}
|
||||
|
||||
# Allow overriding the Flash bank size
|
||||
if { [info exists FLASH_SIZE] } {
|
||||
set _FLASH_SIZE $FLASH_SIZE
|
||||
} else {
|
||||
# autodetect size
|
||||
set _FLASH_SIZE 0
|
||||
}
|
||||
|
||||
#jtag scan chain
|
||||
if { [info exists CPUTAPID] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
@@ -41,7 +49,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
|
||||
|
||||
# flash size will be probed
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
|
||||
flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
|
||||
|
||||
# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
|
||||
adapter_khz 1000
|
||||
|
||||
@@ -82,3 +82,66 @@ $_TARGETNAME configure -event trace-config {
|
||||
# assignment
|
||||
mmw 0xE0042004 0x00000020 0
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# If the HSE was previously enabled and the external clock source
|
||||
# disappeared, RCC_CR.HSERDY can get stuck at 1 and the PLL cannot be
|
||||
# properly switched back to HSI. This situation persists even over a system
|
||||
# reset, including a pin reset via SRST. However, activating the clock
|
||||
# security system will detect the problem and clear HSERDY to 0, which in
|
||||
# turn allows the PLL to switch back to HSI properly. Since we just came
|
||||
# out of reset, HSEON should be 0. If HSERDY is 1, then this situation must
|
||||
# have happened; in that case, activate the clock security system to clear
|
||||
# HSERDY.
|
||||
if {[mrw 0x40023800] & 0x00020000} {
|
||||
mmw 0x40023800 0x00090000 0 ;# RCC_CR = CSSON | HSEON
|
||||
sleep 10 ;# Wait for CSS to fire, if it wants to
|
||||
mmw 0x40023800 0 0x00090000 ;# RCC_CR &= ~CSSON & ~HSEON
|
||||
mww 0x4002380C 0x00800000 ;# RCC_CIR = CSSC
|
||||
sleep 1 ;# Wait for CSSF to clear
|
||||
}
|
||||
|
||||
# If the clock security system fired, it will pend an NMI. A pending NMI
|
||||
# will cause a bad time for any subsequent executing code, such as a
|
||||
# programming algorithm.
|
||||
if {[mrw 0xE000ED04] & 0x80000000} {
|
||||
# ICSR.NMIPENDSET reads as 1. Need to clear it. A pending NMI can’t be
|
||||
# cleared by any normal means (such as ICSR or NVIC). It can only be
|
||||
# cleared by entering the NMI handler or by resetting the processor.
|
||||
echo "[target current]: Clock security system generated NMI. Clearing."
|
||||
|
||||
# Keep the old DEMCR value.
|
||||
set old [mrw 0xE000EDFC]
|
||||
|
||||
# Enable vector catch on reset.
|
||||
mww 0xE000EDFC 0x01000001
|
||||
|
||||
# Issue local reset via AIRCR.
|
||||
mww 0xE000ED0C 0x05FA0001
|
||||
|
||||
# Restore old DEMCR value.
|
||||
mww 0xE000EDFC $old
|
||||
}
|
||||
|
||||
# Configure PLL to boost clock to HSI x 10 (160 MHz)
|
||||
mww 0x40023804 0x08002808 ;# RCC_PLLCFGR 16 Mhz /10 (M) * 128 (N) /2(P)
|
||||
mww 0x40023C00 0x00000107 ;# FLASH_ACR = PRFTBE | 7(Latency)
|
||||
mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
|
||||
sleep 10 ;# Wait for PLL to lock
|
||||
mww 0x40023808 0x00009400 ;# RCC_CFGR_PPRE1 = 5(div 4), PPRE2 = 4(div 2)
|
||||
mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
|
||||
|
||||
# Boost SWD frequency
|
||||
# Do not boost JTAG frequency and slow down JTAG memory access or flash write algo
|
||||
# suffers from DAP WAITs
|
||||
if {[using_jtag]} {
|
||||
[[target current] cget -dap] memaccess 16
|
||||
} {
|
||||
adapter_khz 8000
|
||||
}
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -event reset-start {
|
||||
# Reduce speed since CPU speed will slow down to 16MHz with the reset
|
||||
adapter_khz 2000
|
||||
}
|
||||
|
||||
@@ -0,0 +1,11 @@
|
||||
#
|
||||
# Texas Instruments CC13x0 - ARM Cortex-M3
|
||||
#
|
||||
# http://www.ti.com
|
||||
#
|
||||
|
||||
set CHIPNAME cc13x0
|
||||
set JRC_TAPID 0x0B9BE02F
|
||||
set WORKAREASIZE 0x4000
|
||||
|
||||
source [find target/ti_cc26x0.cfg]
|
||||
@@ -0,0 +1,11 @@
|
||||
#
|
||||
# Texas Instruments CC13x2 - ARM Cortex-M4
|
||||
#
|
||||
# http://www.ti.com
|
||||
#
|
||||
|
||||
set CHIPNAME cc13x2
|
||||
set JRC_TAPID 0x0BB4102F
|
||||
set WORKAREASIZE 0x7000
|
||||
|
||||
source [find target/ti_cc26x0.cfg]
|
||||
Executable → Regular
+26
-14
@@ -1,23 +1,25 @@
|
||||
# Config for Texas Instruments low power SoC CC26xx family
|
||||
|
||||
adapter_khz 100
|
||||
#
|
||||
# Texas Instruments CC26x0 - ARM Cortex-M3
|
||||
#
|
||||
# http://www.ti.com
|
||||
#
|
||||
|
||||
source [find target/icepick.cfg]
|
||||
source [find target/ti-cjtag.cfg]
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME cc26xx
|
||||
set _CHIPNAME cc26x0
|
||||
}
|
||||
|
||||
#
|
||||
# Main DAP
|
||||
#
|
||||
if { [info exists DAP_TAPID] } {
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
set _DAP_TAPID $DAP_TAPID
|
||||
} else {
|
||||
set _DAP_TAPID 0x4BA00477
|
||||
set _DAP_TAPID 0x4BA00477
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
|
||||
jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
|
||||
@@ -26,19 +28,29 @@ jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.
|
||||
# ICEpick-C (JTAG route controller)
|
||||
#
|
||||
if { [info exists JRC_TAPID] } {
|
||||
set _JRC_TAPID $JRC_TAPID
|
||||
set _JRC_TAPID $JRC_TAPID
|
||||
} else {
|
||||
set _JRC_TAPID 0x1B99A02F
|
||||
set _JRC_TAPID 0x0B99A02F
|
||||
}
|
||||
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
|
||||
# A start sequence is needed to change from cJTAG (Compact JTAG) to
|
||||
# 4-pin JTAG before talking via JTAG commands
|
||||
jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
|
||||
# A start sequence is needed to change from 2-pin cJTAG to 4-pin JTAG
|
||||
jtag configure $_CHIPNAME.jrc -event post-reset "ti_cjtag_to_4pin_jtag $_CHIPNAME.jrc"
|
||||
|
||||
#
|
||||
# Cortex-M3 target
|
||||
#
|
||||
set _TARGETNAME $_CHIPNAME.cpu
|
||||
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
|
||||
target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
||||
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
set _WORKAREASIZE 0x4000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME cc26xx 0 0 0 0 $_TARGETNAME
|
||||
|
||||
reset_config srst_only
|
||||
adapter_nsrst_delay 100
|
||||
@@ -0,0 +1,11 @@
|
||||
#
|
||||
# Texas Instruments CC26x2 - ARM Cortex-M4
|
||||
#
|
||||
# http://www.ti.com
|
||||
#
|
||||
|
||||
set CHIPNAME cc26x2
|
||||
set JRC_TAPID 0x0BB4102F
|
||||
set WORKAREASIZE 0x7000
|
||||
|
||||
source [find target/ti_cc26x0.cfg]
|
||||
@@ -1,5 +1,5 @@
|
||||
#
|
||||
# Texas Instruments MSP432P4xx - ARM Cortex-M4F @ up to 48 MHz
|
||||
# Texas Instruments MSP432 - ARM Cortex-M4F @ up to 48 MHz
|
||||
#
|
||||
# http://www.ti.com/MSP432
|
||||
#
|
||||
@@ -7,7 +7,7 @@
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME msp432p4xx
|
||||
set _CHIPNAME msp432
|
||||
}
|
||||
|
||||
if { [info exists CPUTAPID] } {
|
||||
@@ -39,15 +39,13 @@ target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
|
||||
if { [info exists WORKAREASIZE] } {
|
||||
set _WORKAREASIZE $WORKAREASIZE
|
||||
} else {
|
||||
# On MSP432P401x Bank0 (8k) is always powered
|
||||
set _WORKAREASIZE 0x2000
|
||||
set _WORKAREASIZE 0x4000
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 \
|
||||
-work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
|
||||
|
||||
if { ![using_hla] } {
|
||||
cortex_m reset_config sysresetreq
|
||||
}
|
||||
set _FLASHNAME $_CHIPNAME.flash
|
||||
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
|
||||
|
||||
adapter_khz 500
|
||||
reset_config srst_only
|
||||
adapter_nsrst_delay 100
|
||||
Reference in New Issue
Block a user