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target: lakemon: implement assert_reset and deassert_reset

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We're using an I/O port reset by default. The only board currently
supported (Galileo) doesn't have SRST routed on the JTAG connector.

When using 'reset halt', we must rely on Reset Break because our
adapters don't have support for PREQ#/PRDY# signals.

Tested with Intel Galileo GEN2.

Change-Id: Ia406e31c156f8001717d5b6a08bd03f71de790d3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4016
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Felipe Balbi
2017-02-24 15:26:39 +02:00
committed by Paul Fertser
parent 3accbec901
commit 2b44b52478
3 changed files with 160 additions and 3 deletions
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32
src/target/x86_32_common.c
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@@ -1260,6 +1260,38 @@ static int unset_watchpoint(struct target *t, struct watchpoint *wp)
return ERROR_OK;
}
/* after reset breakpoints and watchpoints in memory are not valid anymore and
* debug registers are cleared.
* we can't afford to remove sw breakpoints using the default methods as the
* memory doesn't have the same layout yet and an access might crash the target,
* so we just clear the openocd breakpoints structures.
*/
void x86_32_common_reset_breakpoints_watchpoints(struct target *t)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
struct x86_32_dbg_reg *debug_reg_list = x86_32->hw_break_list;
struct breakpoint *next_b;
struct watchpoint *next_w;
while (t->breakpoints) {
next_b = t->breakpoints->next;
free(t->breakpoints->orig_instr);
free(t->breakpoints);
t->breakpoints = next_b;
}
while (t->watchpoints) {
next_w = t->watchpoints->next;
free(t->watchpoints);
t->watchpoints = next_w;
}
for (int i = 0; i < x86_32->num_hw_bpoints; i++) {
debug_reg_list[i].used = 0;
debug_reg_list[i].bp_value = 0;
}
}
static int read_hw_reg_to_cache(struct target *t, int num)
{
uint32_t reg_value;