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target: lakemon: implement assert_reset and deassert_reset

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We're using an I/O port reset by default. The only board currently
supported (Galileo) doesn't have SRST routed on the JTAG connector.

When using 'reset halt', we must rely on Reset Break because our
adapters don't have support for PREQ#/PRDY# signals.

Tested with Intel Galileo GEN2.

Change-Id: Ia406e31c156f8001717d5b6a08bd03f71de790d3
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Reviewed-on: http://openocd.zylin.com/4016
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Felipe Balbi
2017-02-24 15:26:39 +02:00
committed by Paul Fertser
parent 3accbec901
commit 2b44b52478
3 changed files with 160 additions and 3 deletions
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2
src/target/x86_32_common.h
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@@ -217,6 +217,7 @@ struct x86_32_common {
struct reg_cache *cache;
struct jtag_tap *curr_tap;
uint32_t stored_pc;
int forced_halt_for_reset;
int flush;
/* pm_regs are for probemode save/restore state */
@@ -326,5 +327,6 @@ int x86_32_common_add_breakpoint(struct target *t, struct breakpoint *bp);
int x86_32_common_remove_breakpoint(struct target *t, struct breakpoint *bp);
int x86_32_common_add_watchpoint(struct target *t, struct watchpoint *wp);
int x86_32_common_remove_watchpoint(struct target *t, struct watchpoint *wp);
void x86_32_common_reset_breakpoints_watchpoints(struct target *t);
#endif /* OPENOCD_TARGET_X86_32_COMMON_H */