- only if "reset halt" or "reset init" are issued will the reset vector be set up
- If communication fails during assert between assert/deassert and during assert, warnings are printed. The warning suggests using srst_only if the clock locks up as that would allow the reset vector to be set up before asserting reset. git-svn-id: svn://svn.berlios.de/openocd/trunk@544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@@ -297,7 +297,11 @@ int target_process_reset(struct command_context_s *cmd_ctx)
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target->type->assert_reset(target);
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target = target->next;
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}
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jtag_execute_queue();
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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LOG_WARNING("JTAG communication failed asserting reset.");
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retval = ERROR_OK;
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}
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/* request target halt if necessary, and schedule further action */
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target = targets;
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@@ -330,13 +334,24 @@ int target_process_reset(struct command_context_s *cmd_ctx)
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target = target->next;
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}
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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LOG_WARNING("JTAG communication failed while reset was asserted. Consider using srst_only for reset_config.");
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retval = ERROR_OK;
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}
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target = targets;
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while (target)
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{
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target->type->deassert_reset(target);
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target = target->next;
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}
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jtag_execute_queue();
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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LOG_WARNING("JTAG communication failed while deasserting reset.");
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retval = ERROR_OK;
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}
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LOG_DEBUG("Waiting for halted stated as approperiate");
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