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aarch64: Add support for debugging in HYP mode on ARMv8-A cores

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When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would
throw the following error to GDB on most operations (step, set breakpoint):

	cannot read system control register in this mode

The mode in question is 0x1A, a privilege level 2 mode available on cores
that have the virtualization extensions (such as the Raspi 3).

Note: this mode is only used when running in AArch32 compatibility mode.

Signed-off-by: Lucas Jenss <public@x3ro.de>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2
Reviewed-on: http://openocd.zylin.com/5255
Tested-by: jenkins
Reviewed-by: Lucas Jenß <lucas.jenss@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Lucas
2020-05-17 16:42:39 +01:00
committed by Antonio Borneo
parent 8833c889da
commit 2e6904eef5
3 changed files with 12 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/target/aarch64.c
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@@ -99,12 +99,14 @@ static int aarch64_restore_system_control_reg(struct target *target)
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
case ARM_MODE_HYP:
case ARM_MODE_SYS:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
default:
LOG_INFO("cannot read system control register in this mode");
LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
return ERROR_FAIL;
}
@@ -172,6 +174,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
case ARM_MODE_HYP:
case ARM_MODE_SYS:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
@@ -1033,12 +1036,14 @@ static int aarch64_post_debug_entry(struct target *target)
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
case ARM_MODE_HYP:
case ARM_MODE_SYS:
instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
break;
default:
LOG_INFO("cannot read system control register in this mode");
LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
return ERROR_FAIL;
}