aarch64: Add support for debugging in HYP mode on ARMv8-A cores

When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would
throw the following error to GDB on most operations (step, set breakpoint):

	cannot read system control register in this mode

The mode in question is 0x1A, a privilege level 2 mode available on cores
that have the virtualization extensions (such as the Raspi 3).

Note: this mode is only used when running in AArch32 compatibility mode.

Signed-off-by: Lucas Jenss <public@x3ro.de>
Signed-off-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2
Reviewed-on: http://openocd.zylin.com/5255
Tested-by: jenkins
Reviewed-by: Lucas Jenß <lucas.jenss@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>

src/target/armv8.c

@@ -73,6 +73,10 @@ static const struct {
 		.name = "ABT",
 		.psr = ARM_MODE_ABT,
 	},
+	{
+		.name = "HYP",
+		.psr = ARM_MODE_HYP,
+	},
 	{
 		.name = "SYS",
 		.psr = ARM_MODE_SYS,