Remove whitespace at end of lines, step 1.
- Replace '\s*$' with ''. git-svn-id: svn://svn.berlios.de/openocd/trunk@2379 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@@ -55,7 +55,7 @@ extern char* armv7m_exception_strings[];
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extern char *armv7m_exception_string(int number);
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/* offsets into armv7m core register cache */
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enum
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enum
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{
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ARMV7M_PC = 15,
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ARMV7M_xPSR = 16,
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@@ -78,18 +78,18 @@ typedef struct armv7m_common_s
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int exception_number;
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swjdp_common_t swjdp_info;
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/* Direct processor core register read and writes */
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int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
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int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target_s *target, int num);
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int (*write_core_reg)(struct target_s *target, int num);
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int (*examine_debug_reason)(target_t *target);
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void (*pre_debug_entry)(target_t *target);
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void (*post_debug_entry)(target_t *target);
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void (*pre_restore_context)(target_t *target);
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void (*post_restore_context)(target_t *target);
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@@ -99,7 +99,7 @@ typedef struct armv7m_common_s
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typedef struct armv7m_algorithm_s
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{
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int common_magic;
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enum armv7m_mode core_mode;
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} armv7m_algorithm_t;
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@@ -133,28 +133,28 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
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/* Thumb mode instructions
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*/
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/* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
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* Rd: destination register
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* SYSm: source special register
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*/
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#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
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#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
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/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
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* Rd: source register
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* SYSm: destination special register
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*/
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#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
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#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | (Rn << 8)) | ((0x8800 | SYSm) << 16))
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/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
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/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
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* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
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* Rd: source register
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* IF:
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* IF:
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*/
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#define I_FLAG 2
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#define F_FLAG 1
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#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
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#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
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#define F_FLAG 1
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#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
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#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
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/* Breakpoint (Thumb mode) v5 onwards
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* Im: immediate value used by debugger
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@@ -178,12 +178,12 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
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* List: for each bit in list: store register
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*/
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#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
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/* Load register with PC relative addressing
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* Rd: register to load
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*/
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#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
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#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
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/* Move hi register (Thumb mode)
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* Rd: destination register
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* Rm: source register
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