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David Brownell <david-b@pacbell.net>:

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Initial support for disassembling Thumb2 code.  This works only for
Cortex-M3 cores so far.  Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.

 - Update the 16-bit Thumb decoder:
 
     * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
       by ARMv6.  (It already seems to treat CPY as MOV.)

     * Understand CB, CBNZ, WFI, IT, and other opcodes added by
       in Thumb2.

 - A new Thumb2 instruction decode routine is provided.
 
     * This has a different signature:  pass the target, not the
       instruction, so it can fetch a second halfword when needed.  
       The instruction size is likewise returned to the caller.

     * 32-bit instructions are recognized but not yet decoded.
   
 - Start using the current "UAL" syntax in some cases.  "SWI" is
   renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".

 - Define a new "cortex_m3 disassemble addr count" command to give
   access to this disassembly.

Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch
2009-07-15 23:39:37 +00:00
parent 2ff59c9aaf
commit 309870e414
4 changed files with 300 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

53
src/target/cortex_m3.c
View File

@@ -34,6 +34,7 @@
#include "cortex_m3.h"
#include "target_request.h"
#include "target_type.h"
#include "arm_disassembler.h"
/* cli handling */
@@ -1646,6 +1647,47 @@ int cortex_m3_target_create(struct target_s *target, Jim_Interp *interp)
return ERROR_OK;
}
/*
* REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
* as at least ARM-1156T2. The interesting thing about Cortex-M is
* that *only* Thumb2 disassembly matters. There are also some small
* additions to Thumb2 that are specific to ARMv7-M.
*/
static int
handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
char *cmd, char **args, int argc)
{
int retval = ERROR_OK;
target_t *target = get_current_target(cmd_ctx);
uint32_t address;
unsigned long count;
arm_instruction_t cur_instruction;
if (argc != 2) {
command_print(cmd_ctx,
"usage: cortex_m3 disassemble <address> <count>");
return ERROR_OK;
}
errno = 0;
address = strtoul(args[0], NULL, 0);
if (errno)
return ERROR_FAIL;
count = strtoul(args[1], NULL, 0);
if (errno)
return ERROR_FAIL;
while (count--) {
retval = thumb2_opcode(target, address, &cur_instruction);
if (retval != ERROR_OK)
return retval;
command_print(cmd_ctx, "%s", cur_instruction.text);
address += cur_instruction.instruction_size;
}
return ERROR_OK;
}
int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
@@ -1653,8 +1695,15 @@ int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
retval = armv7m_register_commands(cmd_ctx);
cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands");
register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']");
cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
NULL, COMMAND_ANY, "cortex_m3 specific commands");
register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
handle_cortex_m3_disassemble_command, COMMAND_EXEC,
"disassemble Thumb2 instructions <address> <count>");
register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
"mask cortex_m3 interrupts ['on'|'off']");
return retval;
}