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OpenOCD: fix code indentation

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Fix checkpatch errors

	ERROR:SUSPECT_CODE_INDENT: suspect code indent for
	conditional statements

Change-Id: I94d4fa5720c25dd2fb0334a824cd9026babcce4e
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8497
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2024-09-16 13:45:19 +02:00
parent 8e89a8af63
commit 3099547069
17 changed files with 72 additions and 83 deletions
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6
src/target/aarch64.c
View File

@@ -2908,9 +2908,9 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *
pc = (struct aarch64_private_config *)target->private_config;
if (!pc) {
pc = calloc(1, sizeof(struct aarch64_private_config));
pc->adiv5_config.ap_num = DP_APSEL_INVALID;
target->private_config = pc;
pc = calloc(1, sizeof(struct aarch64_private_config));
pc->adiv5_config.ap_num = DP_APSEL_INVALID;
target->private_config = pc;
}
/*

18
src/target/arc.c
View File

@@ -388,7 +388,7 @@ static int arc_build_reg_cache(struct target *target)
}
list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, i));
LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
reg_list[i].name, reg_list[i].group,
@@ -464,7 +464,7 @@ static int arc_build_bcr_reg_cache(struct target *target)
}
list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
CHECK_RETVAL(arc_init_reg(target, &reg_list[i], reg_desc, gdb_regnum));
/* BCRs always semantically, they are just read-as-zero, if there is
* not real register. */
reg_list[i].exist = true;
@@ -719,14 +719,14 @@ static int arc_configure(struct target *target)
LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");
/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
CHECK_RETVAL(arc_configure_dccm(target));
if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true)
&& arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
CHECK_RETVAL(arc_configure_dccm(target));
/* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
CHECK_RETVAL(arc_configure_iccm(target));
if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true)
&& arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
CHECK_RETVAL(arc_configure_iccm(target));
return ERROR_OK;
}
@@ -1067,9 +1067,7 @@ static int arc_poll(struct target *target)
LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
"target is still running");
}
} else if (target->state == TARGET_DEBUG_RUNNING) {
target->state = TARGET_HALTED;
LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");

22
src/target/armv4_5.c
View File

@@ -1301,11 +1301,11 @@ int arm_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
(*reg_list)[i] = arm_reg_current(arm, i);
(*reg_list)[i] = arm_reg_current(arm, i);
/* For GDB compatibility, take FPA registers size into account and zero-fill it*/
for (i = 16; i < 24; i++)
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[25] = arm->cpsr;
@@ -1330,25 +1330,25 @@ int arm_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < 16; i++)
(*reg_list)[i] = arm_reg_current(arm, i);
(*reg_list)[i] = arm_reg_current(arm, i);
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
int reg_index = arm->core_cache->reg_list[i].number;
if (arm_core_regs[i].mode == ARM_MODE_MON
if (arm_core_regs[i].mode == ARM_MODE_MON
&& arm->core_type != ARM_CORE_TYPE_SEC_EXT
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
if (arm_core_regs[i].mode == ARM_MODE_HYP
continue;
if (arm_core_regs[i].mode == ARM_MODE_HYP
&& arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
continue;
(*reg_list)[reg_index] = &arm->core_cache->reg_list[i];
}
/* When we supply the target description, there is no need for fake FPA */
for (i = 16; i < 24; i++) {
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[i]->size = 0;
(*reg_list)[i] = &arm_gdb_dummy_fp_reg;
(*reg_list)[i]->size = 0;
}
(*reg_list)[24] = &arm_gdb_dummy_fps_reg;
(*reg_list)[24]->size = 0;

9
src/target/armv7a_mmu.c
View File

@@ -260,8 +260,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
/* skip empty entries in the first level table */
if ((first_lvl_descriptor & 3) == 0) {
pt_idx++;
} else
if ((first_lvl_descriptor & 0x40002) == 2) {
} else if ((first_lvl_descriptor & 0x40002) == 2) {
/* section descriptor */
uint32_t va_range = 1024*1024-1; /* 1MB range */
uint32_t va_start = pt_idx << 20;
@@ -273,8 +272,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
LOG_USER("SECT: VA[%8.8"PRIx32" -- %8.8"PRIx32"]: PA[%8.8"PRIx32" -- %8.8"PRIx32"] %s",
va_start, va_end, pa_start, pa_end, l1_desc_bits_to_string(first_lvl_descriptor, afe));
pt_idx++;
} else
if ((first_lvl_descriptor & 0x40002) == 0x40002) {
} else if ((first_lvl_descriptor & 0x40002) == 0x40002) {
/* supersection descriptor */
uint32_t va_range = 16*1024*1024-1; /* 16MB range */
uint32_t va_start = pt_idx << 20;
@@ -310,8 +308,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
if ((second_lvl_descriptor & 3) == 0) {
/* skip entry */
pt2_idx++;
} else
if ((second_lvl_descriptor & 3) == 1) {
} else if ((second_lvl_descriptor & 3) == 1) {
/* large page */
uint32_t va_range = 64*1024-1; /* 64KB range */
uint32_t va_start = (pt_idx << 20) + (pt2_idx << 12);

4
src/target/armv8.c
View File

@@ -1966,7 +1966,7 @@ int armv8_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < *reg_list_size; i++)
(*reg_list)[i] = armv8_reg_current(arm, i);
(*reg_list)[i] = armv8_reg_current(arm, i);
return ERROR_OK;
case REG_CLASS_ALL:
@@ -1974,7 +1974,7 @@ int armv8_get_gdb_reg_list(struct target *target,
*reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
for (i = 0; i < *reg_list_size; i++)
(*reg_list)[i] = armv8_reg_current(arm, i);
(*reg_list)[i] = armv8_reg_current(arm, i);
return ERROR_OK;

29
src/target/cortex_a.c
View File

@@ -1324,21 +1324,21 @@ static int cortex_a_set_breakpoint(struct target *target,
brp_list[brp_i].value);
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
/* length == 2: Thumb breakpoint */
if (breakpoint->length == 2)
if (breakpoint->length == 2) {
/* length == 2: Thumb breakpoint */
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
else
/* length == 3: Thumb-2 breakpoint, actual encoding is
* a regular Thumb BKPT instruction but we replace a
* 32bit Thumb-2 instruction, so fix-up the breakpoint
* length
*/
if (breakpoint->length == 3) {
} else if (breakpoint->length == 3) {
/* length == 3: Thumb-2 breakpoint, actual encoding is
* a regular Thumb BKPT instruction but we replace a
* 32bit Thumb-2 instruction, so fix-up the breakpoint
* length
*/
buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
breakpoint->length = 4;
} else
} else {
/* length == 4, normal ARM breakpoint */
buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
}
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFE,
@@ -1348,8 +1348,7 @@ static int cortex_a_set_breakpoint(struct target *target,
return retval;
/* make sure data cache is cleaned & invalidated down to PoC */
armv7a_cache_flush_virt(target, breakpoint->address,
breakpoint->length);
armv7a_cache_flush_virt(target, breakpoint->address, breakpoint->length);
retval = target_write_memory(target,
breakpoint->address & 0xFFFFFFFE,
@@ -1358,10 +1357,8 @@ static int cortex_a_set_breakpoint(struct target *target,
return retval;
/* update i-cache at breakpoint location */
armv7a_l1_d_cache_inval_virt(target, breakpoint->address,
breakpoint->length);
armv7a_l1_i_cache_inval_virt(target, breakpoint->address,
breakpoint->length);
armv7a_l1_d_cache_inval_virt(target, breakpoint->address, breakpoint->length);
armv7a_l1_i_cache_inval_virt(target, breakpoint->address, breakpoint->length);
breakpoint->is_set = true;
}

2
src/target/mips32.c
View File

@@ -2357,7 +2357,7 @@ COMMAND_HANDLER(mips32_handle_scan_delay_command)
if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
else if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
return ERROR_COMMAND_SYNTAX_ERROR;
command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {

2
src/target/mips_m4k.c
View File

@@ -1397,7 +1397,7 @@ COMMAND_HANDLER(mips_m4k_handle_scan_delay_command)
if (CMD_ARGC == 1)
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], ejtag_info->scan_delay);
else if (CMD_ARGC > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
return ERROR_COMMAND_SYNTAX_ERROR;
command_print(CMD, "scan delay: %d nsec", ejtag_info->scan_delay);
if (ejtag_info->scan_delay >= MIPS32_SCAN_DELAY_LEGACY_MODE) {

10
src/target/stm8.c
View File

@@ -689,15 +689,13 @@ static int stm8_write_flash(struct target *target, enum mem_type type,
if (stm8->flash_ncr2)
stm8_write_u8(target, stm8->flash_ncr2, ~(PRG + opt));
blocksize = blocksize_param;
} else
if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
} else if ((bytecnt >= 4) && ((address & 0x3) == 0)) {
if (stm8->flash_cr2)
stm8_write_u8(target, stm8->flash_cr2, WPRG + opt);
if (stm8->flash_ncr2)
stm8_write_u8(target, stm8->flash_ncr2, ~(WPRG + opt));
blocksize = 4;
} else
if (blocksize != 1) {
} else if (blocksize != 1) {
if (stm8->flash_cr2)
stm8_write_u8(target, stm8->flash_cr2, opt);
if (stm8->flash_ncr2)
@@ -1552,8 +1550,8 @@ static int stm8_set_watchpoint(struct target *target,
}
if (watchpoint->length != 1) {
LOG_ERROR("Only watchpoints of length 1 are supported");
return ERROR_TARGET_UNALIGNED_ACCESS;
LOG_ERROR("Only watchpoints of length 1 are supported");
return ERROR_TARGET_UNALIGNED_ACCESS;
}
enum hw_break_type enable = 0;