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TCL: fix non TCL comments

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End of line comments fixed with ';' before '#'.
Added few additional 'space' to keep indentation in
multi-line comments.

Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Antonio Borneo
2010-12-19 01:22:53 +08:00
committed by Øyvind Harboe
parent af3f77a177
commit 30da7c67ce
28 changed files with 724 additions and 724 deletions
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tcl/board/atmel_at91sam9260-ek.cfg
+22 -22
View File
@@ -28,36 +28,36 @@ $_TARGETNAME configure -event reset-start {
}
$_TARGETNAME configure -event reset-init {
mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
mww 0xfffffd44 0x00008000 ;# WDT_MR : disable watchdog
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
sleep 20 # wait 20 ms
mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
sleep 10 # wait 10 ms
mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
sleep 20 # wait 20 ms
mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
sleep 10 # wait 10 ms
mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
sleep 10 # wait 10 ms
mww 0xfffffc20 0x00004001 ;# CKGR_MOR : enable the main oscillator
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000001 ;# PMC_MCKR : switch to main oscillator
sleep 10 ;# wait 10 ms
mww 0xfffffc28 0x2060bf09 ;# CKGR_PLLAR: Set PLLA Register for 198.656 MHz
sleep 20 ;# wait 20 ms
mww 0xfffffc30 0x00000101 ;# PMC_MCKR : Select prescaler (divide by 2)
sleep 10 ;# wait 10 ms
mww 0xfffffc30 0x00000102 ;# PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
sleep 10 ;# wait 10 ms
# Increase JTAG Speed to 6 MHz if RCLK is not supported
jtag_rclk 6000
arm7_9 dcc_downloads enable # Enable faster DCC downloads
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
mww 0xfffff870 0xffff0000 ;# PIO_ASR : Select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 ;# PIO_PDR : Disable PIO function for D15..D31
mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
mww 0xffffef1c 0x00010002 ;# EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
mww 0xffffea08 0x85227259 ;# SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
mww 0xffffea00 0x1 ;# SDRAMC_MR : issue a NOP command
mww 0x20000000 0
mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0xffffea00 0x2 ;# SDRAMC_MR : issue an 'All Banks Precharge' command
mww 0x20000000 0
mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0xffffea00 0x4 ;# SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
@@ -73,9 +73,9 @@ $_TARGETNAME configure -event reset-init {
mww 0x20000000 0
mww 0xffffea00 0x4
mww 0x20000000 0
mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
mww 0xffffea00 0x3 ;# SDRAMC_MR : issue a 'Load Mode Register' command
mww 0x20000000 0
mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
mww 0xffffea00 0x0 ;# SDRAMC_MR : normal mode
mww 0x20000000 0
mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
mww 0xffffea04 0x2b6 ;# SDRAMC_TR : Set refresh timer count to 7us
}