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ARM: rename ARMV4_5_STATE_* as ARM_STATE_*

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Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
This commit is contained in:
David Brownell
2009-12-04 19:14:48 -08:00
parent f67f6fe5bb
commit 31e3ea7c19
18 changed files with 77 additions and 77 deletions
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2
src/flash/nor/aduc702x.c
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@@ -243,7 +243,7 @@ static int aduc702x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);

4
src/flash/nor/cfi.c
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@@ -1087,7 +1087,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint3
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
/* If we are setting up the write_algorith, we need target_code_src */
/* if not we only need target_code_size. */
@@ -1410,7 +1410,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, ui
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
int target_code_size;
const uint32_t *target_code_src;

2
src/flash/nor/ecos.c
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@@ -212,7 +212,7 @@ static int runCode(struct ecosflash_flash_bank *info,
struct armv4_5_algorithm armv4_5_info;
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);

2
src/flash/nor/lpc2000.c
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@@ -294,7 +294,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, int code, uint32_t param_ta
case lpc2000_v2:
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
iap_entry_point = 0x7ffffff1;
break;
default:

2
src/flash/nor/lpc2900.c
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@@ -1425,7 +1425,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer,
/* Execute algorithm, assume breakpoint for last instruction */
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
retval = target_run_algorithm(target, 0, NULL, 5, reg_params,
(warea->address) + buffer_size,

2
src/flash/nor/str7x.c
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@@ -373,7 +373,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);

2
src/flash/nor/str9x.c
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@@ -410,7 +410,7 @@ static int str9x_write_block(struct flash_bank *bank,
armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
armv4_5_info.core_state = ARM_STATE_ARM;
init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);