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target/riscv: check nextdm address in abits range

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Imported from
https://github.com/riscv-collab/riscv-openocd/pull/1257
developed by Mark Zhuang <mark.zhuang@spacemit.com>

When abits not correctly configured, we hope to detect it
as soon as possible.

Change-Id: I0b7b170c39761fb531dda0747f88ace3f39ae03b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/9141
Reviewed-by: Evgeniy Naydanov <evgeniy.naydanov@syntacore.com>
Tested-by: jenkins
This commit is contained in:
Tomas Vanek
2025-05-15 14:58:07 +08:00
parent 4447fa4c98
commit 3483756cba
1 changed files with 7 additions and 0 deletions
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7
src/target/riscv/riscv-013.c
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@@ -538,6 +538,7 @@ static bool check_dbgbase_exists(struct target *target)
{ {
uint32_t next_dm = 0; uint32_t next_dm = 0;
unsigned int count = 1; unsigned int count = 1;
riscv013_info_t *info = get_info(target);
LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase); LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase);
while (1) { while (1) {
@@ -552,6 +553,12 @@ static bool check_dbgbase_exists(struct target *target)
LOG_TARGET_ERROR(target, "Reached the end of DM chain (detected %u DMs in total).", count); LOG_TARGET_ERROR(target, "Reached the end of DM chain (detected %u DMs in total).", count);
break; break;
} }
if (next_dm >> info->abits) {
LOG_TARGET_ERROR(target, "The address of the next Debug Module does not fit into %u bits, "
"which is the width of the DMI bus address. This is a HW bug",
info->abits);
break;
}
/* Safety: Avoid looping forever in case of buggy nextdm values in the hardware. */ /* Safety: Avoid looping forever in case of buggy nextdm values in the hardware. */
if (count++ > RISCV_MAX_DMS) { if (count++ > RISCV_MAX_DMS) {
LOG_TARGET_ERROR(target, "Supporting no more than %d DMs on a DMI bus. Aborting", RISCV_MAX_DMS); LOG_TARGET_ERROR(target, "Supporting no more than %d DMs on a DMI bus. Aborting", RISCV_MAX_DMS);