flash/nor/fespi: algorithm, large address, errors
* Move more smarts into the target algorithm code, and rewrite that in C so it's easier to understand/maintain. * Support >24-bit addresses. * Check for errors. Change-Id: I3b1a143589fe6defafb8f95820aa682acc9646e7 Signed-off-by: Tim Newsome <tim@sifive.com> Reviewed-on: https://review.openocd.org/c/openocd/+/6679 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Tim Newsome
committed by
Antonio Borneo
Antonio Borneo
parent
15110b2b5b
commit
35f284fe7c
@@ -337,6 +337,11 @@ static int fespi_erase_sector(struct flash_bank *bank, int sector)
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if (retval != ERROR_OK)
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return retval;
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sector = bank->sectors[sector].offset;
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if (bank->size > 0x1000000) {
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retval = fespi_tx(bank, sector >> 24);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = fespi_tx(bank, sector >> 16);
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if (retval != ERROR_OK)
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return retval;
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@@ -435,32 +440,38 @@ static int fespi_protect(struct flash_bank *bank, int set,
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static int slow_fespi_write_buffer(struct flash_bank *bank,
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const uint8_t *buffer, uint32_t offset, uint32_t len)
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{
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t ii;
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if (offset & 0xFF000000) {
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LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%" PRIx32,
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offset);
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return ERROR_FAIL;
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}
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/* TODO!!! assert that len < page size */
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fespi_tx(bank, SPIFLASH_WRITE_ENABLE);
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fespi_txwm_wait(bank);
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if (fespi_tx(bank, SPIFLASH_WRITE_ENABLE) != ERROR_OK)
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return ERROR_FAIL;
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if (fespi_txwm_wait(bank) != ERROR_OK)
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return ERROR_FAIL;
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if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD) != ERROR_OK)
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return ERROR_FAIL;
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fespi_tx(bank, SPIFLASH_PAGE_PROGRAM);
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if (fespi_tx(bank, fespi_info->dev->pprog_cmd) != ERROR_OK)
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return ERROR_FAIL;
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fespi_tx(bank, offset >> 16);
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fespi_tx(bank, offset >> 8);
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fespi_tx(bank, offset);
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if (bank->size > 0x1000000 && fespi_tx(bank, offset >> 24) != ERROR_OK)
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return ERROR_FAIL;
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if (fespi_tx(bank, offset >> 16) != ERROR_OK)
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return ERROR_FAIL;
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if (fespi_tx(bank, offset >> 8) != ERROR_OK)
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return ERROR_FAIL;
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if (fespi_tx(bank, offset) != ERROR_OK)
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return ERROR_FAIL;
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for (ii = 0; ii < len; ii++)
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fespi_tx(bank, buffer[ii]);
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for (ii = 0; ii < len; ii++) {
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if (fespi_tx(bank, buffer[ii]) != ERROR_OK)
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return ERROR_FAIL;
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}
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fespi_txwm_wait(bank);
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if (fespi_txwm_wait(bank) != ERROR_OK)
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return ERROR_FAIL;
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if (fespi_write_reg(bank, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO) != ERROR_OK)
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return ERROR_FAIL;
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@@ -470,273 +481,24 @@ static int slow_fespi_write_buffer(struct flash_bank *bank,
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return ERROR_OK;
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}
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static const uint8_t algorithm_bin[] = {
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#include "../../../contrib/loaders/flash/fespi/fespi.inc"
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};
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#define STEP_EXIT 4
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#define STEP_TX 8
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#define STEP_TXWM_WAIT 12
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#define STEP_WRITE_REG 16
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#define STEP_WIP_WAIT 20
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#define STEP_SET_DIR 24
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#define STEP_NOP 0xff
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struct algorithm_steps {
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unsigned size;
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unsigned used;
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uint8_t **steps;
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static const uint8_t riscv32_bin[] = {
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#include "../../../contrib/loaders/flash/fespi/riscv32_fespi.inc"
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};
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static struct algorithm_steps *as_new(void)
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{
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struct algorithm_steps *as = calloc(1, sizeof(struct algorithm_steps));
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as->size = 8;
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as->steps = malloc(as->size * sizeof(as->steps[0]));
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return as;
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}
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static struct algorithm_steps *as_delete(struct algorithm_steps *as)
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{
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for (unsigned step = 0; step < as->used; step++) {
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free(as->steps[step]);
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as->steps[step] = NULL;
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}
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free(as->steps);
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free(as);
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return NULL;
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}
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static int as_empty(struct algorithm_steps *as)
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{
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for (unsigned s = 0; s < as->used; s++) {
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if (as->steps[s][0] != STEP_NOP)
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return 0;
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}
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return 1;
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}
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/* Return size of compiled program. */
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static unsigned as_compile(struct algorithm_steps *as, uint8_t *target,
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unsigned target_size)
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{
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unsigned offset = 0;
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bool finish_early = false;
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for (unsigned s = 0; s < as->used && !finish_early; s++) {
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unsigned bytes_left = target_size - offset;
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switch (as->steps[s][0]) {
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case STEP_NOP:
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break;
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case STEP_TX:
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{
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unsigned size = as->steps[s][1];
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if (size + 3 > bytes_left) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], size + 2);
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offset += size + 2;
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break;
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}
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case STEP_WRITE_REG:
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if (bytes_left < 4) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], 3);
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offset += 3;
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break;
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case STEP_SET_DIR:
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if (bytes_left < 3) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], 2);
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offset += 2;
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break;
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case STEP_TXWM_WAIT:
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case STEP_WIP_WAIT:
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if (bytes_left < 2) {
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finish_early = true;
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break;
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}
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memcpy(target + offset, as->steps[s], 1);
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offset += 1;
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break;
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default:
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assert(0);
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}
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if (!finish_early)
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as->steps[s][0] = STEP_NOP;
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}
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assert(offset + 1 <= target_size);
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target[offset++] = STEP_EXIT;
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LOG_DEBUG("%d-byte program:", offset);
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for (unsigned i = 0; i < offset;) {
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char buf[80];
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for (unsigned x = 0; i < offset && x < 16; x++, i++)
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sprintf(buf + x*3, "%02x ", target[i]);
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LOG_DEBUG("%s", buf);
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}
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return offset;
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}
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static void as_add_step(struct algorithm_steps *as, uint8_t *step)
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{
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if (as->used == as->size) {
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as->size *= 2;
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as->steps = realloc(as->steps, sizeof(as->steps[0]) * as->size);
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LOG_DEBUG("Increased size to 0x%x", as->size);
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}
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as->steps[as->used] = step;
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as->used++;
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}
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static void as_add_tx(struct algorithm_steps *as, unsigned count, const uint8_t *data)
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{
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LOG_DEBUG("count=%d", count);
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while (count > 0) {
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unsigned step_count = MIN(count, 255);
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uint8_t *step = malloc(step_count + 2);
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step[0] = STEP_TX;
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step[1] = step_count;
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memcpy(step + 2, data, step_count);
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as_add_step(as, step);
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data += step_count;
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count -= step_count;
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}
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}
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static void as_add_tx1(struct algorithm_steps *as, uint8_t byte)
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{
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uint8_t data[1];
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data[0] = byte;
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as_add_tx(as, 1, data);
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}
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static void as_add_write_reg(struct algorithm_steps *as, uint8_t offset, uint8_t data)
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{
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uint8_t *step = malloc(3);
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step[0] = STEP_WRITE_REG;
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step[1] = offset;
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step[2] = data;
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as_add_step(as, step);
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}
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static void as_add_txwm_wait(struct algorithm_steps *as)
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{
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uint8_t *step = malloc(1);
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step[0] = STEP_TXWM_WAIT;
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as_add_step(as, step);
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}
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static void as_add_wip_wait(struct algorithm_steps *as)
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{
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uint8_t *step = malloc(1);
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step[0] = STEP_WIP_WAIT;
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as_add_step(as, step);
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}
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static void as_add_set_dir(struct algorithm_steps *as, bool dir)
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{
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uint8_t *step = malloc(2);
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step[0] = STEP_SET_DIR;
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step[1] = FESPI_FMT_DIR(dir);
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as_add_step(as, step);
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}
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/* This should write something less than or equal to a page.*/
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static int steps_add_buffer_write(struct algorithm_steps *as,
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const uint8_t *buffer, uint32_t chip_offset, uint32_t len)
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{
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if (chip_offset & 0xFF000000) {
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LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%" PRIx32,
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chip_offset);
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return ERROR_FAIL;
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}
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as_add_tx1(as, SPIFLASH_WRITE_ENABLE);
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as_add_txwm_wait(as);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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uint8_t setup[] = {
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SPIFLASH_PAGE_PROGRAM,
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chip_offset >> 16,
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chip_offset >> 8,
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chip_offset,
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};
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as_add_tx(as, sizeof(setup), setup);
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as_add_tx(as, len, buffer);
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as_add_txwm_wait(as);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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/* fespi_wip() */
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as_add_set_dir(as, FESPI_DIR_RX);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD);
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as_add_wip_wait(as);
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as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_AUTO);
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as_add_set_dir(as, FESPI_DIR_TX);
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return ERROR_OK;
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}
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static int steps_execute(struct algorithm_steps *as,
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struct flash_bank *bank, struct working_area *algorithm_wa,
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struct working_area *data_wa)
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{
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struct target *target = bank->target;
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t ctrl_base = fespi_info->ctrl_base;
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int xlen = riscv_xlen(target);
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struct reg_param reg_params[2];
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init_reg_param(®_params[0], "a0", xlen, PARAM_OUT);
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init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
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buf_set_u64(reg_params[0].value, 0, xlen, ctrl_base);
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buf_set_u64(reg_params[1].value, 0, xlen, data_wa->address);
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int retval = ERROR_OK;
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while (!as_empty(as)) {
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keep_alive();
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uint8_t *data_buf = malloc(data_wa->size);
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unsigned bytes = as_compile(as, data_buf, data_wa->size);
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retval = target_write_buffer(target, data_wa->address, bytes,
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data_buf);
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free(data_buf);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to write data to " TARGET_ADDR_FMT ": %d",
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data_wa->address, retval);
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goto exit;
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}
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retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
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algorithm_wa->address, algorithm_wa->address + 4,
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10000, NULL);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
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algorithm_wa->address, retval);
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goto exit;
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}
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}
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exit:
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destroy_reg_param(®_params[1]);
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destroy_reg_param(®_params[0]);
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return retval;
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}
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static const uint8_t riscv64_bin[] = {
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#include "../../../contrib/loaders/flash/fespi/riscv64_fespi.inc"
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};
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static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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uint32_t offset, uint32_t count)
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{
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struct target *target = bank->target;
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struct fespi_flash_bank *fespi_info = bank->driver_priv;
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uint32_t cur_count, page_size, page_offset;
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uint32_t cur_count, page_size;
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int retval = ERROR_OK;
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LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
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__func__, offset, count);
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LOG_DEBUG("bank->size=0x%x offset=0x%08" PRIx32 " count=0x%08" PRIx32,
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bank->size, offset, count);
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if (target->state != TARGET_HALTED) {
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LOG_ERROR("Target not halted");
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@@ -761,80 +523,142 @@ static int fespi_write(struct flash_bank *bank, const uint8_t *buffer,
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}
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}
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struct working_area *algorithm_wa;
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if (target_alloc_working_area(target, sizeof(algorithm_bin),
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&algorithm_wa) != ERROR_OK) {
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LOG_WARNING("Couldn't allocate %zd-byte working area.",
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sizeof(algorithm_bin));
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algorithm_wa = NULL;
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unsigned int xlen = riscv_xlen(target);
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struct working_area *algorithm_wa = NULL;
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struct working_area *data_wa = NULL;
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const uint8_t *bin;
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size_t bin_size;
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if (xlen == 32) {
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bin = riscv32_bin;
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bin_size = sizeof(riscv32_bin);
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} else {
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bin = riscv64_bin;
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bin_size = sizeof(riscv64_bin);
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}
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unsigned data_wa_size = 0;
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if (target_alloc_working_area(target, bin_size, &algorithm_wa) == ERROR_OK) {
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retval = target_write_buffer(target, algorithm_wa->address,
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sizeof(algorithm_bin), algorithm_bin);
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bin_size, bin);
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if (retval != ERROR_OK) {
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LOG_ERROR("Failed to write code to " TARGET_ADDR_FMT ": %d",
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algorithm_wa->address, retval);
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target_free_working_area(target, algorithm_wa);
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algorithm_wa = NULL;
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}
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}
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struct working_area *data_wa = NULL;
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unsigned data_wa_size = 2 * count;
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while (1) {
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if (data_wa_size < 128) {
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LOG_WARNING("Couldn't allocate data working area.");
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target_free_working_area(target, algorithm_wa);
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algorithm_wa = NULL;
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} else {
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data_wa_size = MIN(target_get_working_area_avail(target), count);
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if (data_wa_size < 128) {
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LOG_WARNING("Couldn't allocate data working area.");
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target_free_working_area(target, algorithm_wa);
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algorithm_wa = NULL;
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} else if (target_alloc_working_area(target, data_wa_size, &data_wa) != ERROR_OK) {
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target_free_working_area(target, algorithm_wa);
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algorithm_wa = NULL;
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}
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}
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if (target_alloc_working_area_try(target, data_wa_size, &data_wa) ==
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ERROR_OK) {
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break;
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}
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data_wa_size /= 2;
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} else {
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LOG_WARNING("Couldn't allocate %zd-byte working area.", bin_size);
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algorithm_wa = NULL;
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}
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/* If no valid page_size, use reasonable default. */
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page_size = fespi_info->dev->pagesize ?
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fespi_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
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fespi_txwm_wait(bank);
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if (algorithm_wa) {
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struct reg_param reg_params[6];
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init_reg_param(®_params[0], "a0", xlen, PARAM_IN_OUT);
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init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
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init_reg_param(®_params[2], "a2", xlen, PARAM_OUT);
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init_reg_param(®_params[3], "a3", xlen, PARAM_OUT);
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init_reg_param(®_params[4], "a4", xlen, PARAM_OUT);
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init_reg_param(®_params[5], "a5", xlen, PARAM_OUT);
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/* Disable Hardware accesses*/
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if (fespi_disable_hw_mode(bank) != ERROR_OK)
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return ERROR_FAIL;
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while (count > 0) {
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cur_count = MIN(count, data_wa_size);
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buf_set_u64(reg_params[0].value, 0, xlen, fespi_info->ctrl_base);
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buf_set_u64(reg_params[1].value, 0, xlen, page_size);
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buf_set_u64(reg_params[2].value, 0, xlen, data_wa->address);
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buf_set_u64(reg_params[3].value, 0, xlen, offset);
|
||||
buf_set_u64(reg_params[4].value, 0, xlen, cur_count);
|
||||
buf_set_u64(reg_params[5].value, 0, xlen,
|
||||
fespi_info->dev->pprog_cmd | (bank->size > 0x1000000 ? 0x100 : 0));
|
||||
|
||||
struct algorithm_steps *as = as_new();
|
||||
retval = target_write_buffer(target, data_wa->address, cur_count,
|
||||
buffer);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_DEBUG("Failed to write %d bytes to " TARGET_ADDR_FMT ": %d",
|
||||
cur_count, data_wa->address, retval);
|
||||
goto err;
|
||||
}
|
||||
|
||||
/* poll WIP */
|
||||
retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
LOG_DEBUG("write(ctrl_base=0x%" TARGET_PRIxADDR ", page_size=0x%x, "
|
||||
"address=0x%" TARGET_PRIxADDR ", offset=0x%" PRIx32
|
||||
", count=0x%" PRIx32 "), buffer=%02x %02x %02x %02x %02x %02x ..." PRIx32,
|
||||
fespi_info->ctrl_base, page_size, data_wa->address, offset, cur_count,
|
||||
buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5]);
|
||||
retval = target_run_algorithm(target, 0, NULL,
|
||||
ARRAY_SIZE(reg_params), reg_params,
|
||||
algorithm_wa->address, 0, cur_count * 2, NULL);
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("Failed to execute algorithm at " TARGET_ADDR_FMT ": %d",
|
||||
algorithm_wa->address, retval);
|
||||
goto err;
|
||||
}
|
||||
|
||||
page_offset = offset % page_size;
|
||||
/* central part, aligned words */
|
||||
while (count > 0) {
|
||||
/* clip block at page boundary */
|
||||
if (page_offset + count > page_size)
|
||||
cur_count = page_size - page_offset;
|
||||
else
|
||||
cur_count = count;
|
||||
uint64_t algorithm_result = buf_get_u64(reg_params[0].value, 0, xlen);
|
||||
if (algorithm_result != 0) {
|
||||
LOG_ERROR("Algorithm returned error %" PRId64, algorithm_result);
|
||||
retval = ERROR_FAIL;
|
||||
goto err;
|
||||
}
|
||||
|
||||
if (algorithm_wa)
|
||||
retval = steps_add_buffer_write(as, buffer, offset, cur_count);
|
||||
else
|
||||
retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
|
||||
buffer += cur_count;
|
||||
offset += cur_count;
|
||||
count -= cur_count;
|
||||
}
|
||||
|
||||
target_free_working_area(target, data_wa);
|
||||
target_free_working_area(target, algorithm_wa);
|
||||
|
||||
} else {
|
||||
fespi_txwm_wait(bank);
|
||||
|
||||
/* Disable Hardware accesses*/
|
||||
if (fespi_disable_hw_mode(bank) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
|
||||
/* poll WIP */
|
||||
retval = fespi_wip(bank, FESPI_PROBE_TIMEOUT);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
page_offset = 0;
|
||||
buffer += cur_count;
|
||||
offset += cur_count;
|
||||
count -= cur_count;
|
||||
uint32_t page_offset = offset % page_size;
|
||||
/* central part, aligned words */
|
||||
while (count > 0) {
|
||||
/* clip block at page boundary */
|
||||
if (page_offset + count > page_size)
|
||||
cur_count = page_size - page_offset;
|
||||
else
|
||||
cur_count = count;
|
||||
|
||||
retval = slow_fespi_write_buffer(bank, buffer, offset, cur_count);
|
||||
if (retval != ERROR_OK)
|
||||
goto err;
|
||||
|
||||
page_offset = 0;
|
||||
buffer += cur_count;
|
||||
offset += cur_count;
|
||||
count -= cur_count;
|
||||
}
|
||||
|
||||
/* Switch to HW mode before return to prompt */
|
||||
if (fespi_enable_hw_mode(bank) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
}
|
||||
|
||||
if (algorithm_wa)
|
||||
retval = steps_execute(as, bank, algorithm_wa, data_wa);
|
||||
return ERROR_OK;
|
||||
|
||||
err:
|
||||
if (algorithm_wa) {
|
||||
@@ -842,11 +666,10 @@ err:
|
||||
target_free_working_area(target, algorithm_wa);
|
||||
}
|
||||
|
||||
as_delete(as);
|
||||
|
||||
/* Switch to HW mode before return to prompt */
|
||||
if (fespi_enable_hw_mode(bank) != ERROR_OK)
|
||||
return ERROR_FAIL;
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
@@ -976,8 +799,6 @@ static int fespi_probe(struct flash_bank *bank)
|
||||
|
||||
if (bank->size <= (1UL << 16))
|
||||
LOG_WARNING("device needs 2-byte addresses - not implemented");
|
||||
if (bank->size > (1UL << 24))
|
||||
LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
|
||||
|
||||
/* if no sectors, treat whole bank as single sector */
|
||||
sectorsize = fespi_info->dev->sectorsize ?
|
||||
|
||||
Reference in New Issue
Block a user