build: cleanup src/target directory
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
This commit is contained in:
@@ -20,6 +20,7 @@
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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#ifdef HAVE_CONFIG_H
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#include "config.h"
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#endif
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@@ -54,14 +55,12 @@ static int arm720t_scan_cp15(struct target *target,
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buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
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if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
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{
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retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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}
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if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
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{
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retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
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if (retval != ERROR_OK)
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return retval;
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}
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fields[0].num_bits = 1;
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fields[0].out_value = &instruction_buf;
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@@ -71,24 +70,20 @@ static int arm720t_scan_cp15(struct target *target,
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fields[1].out_value = out_buf;
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fields[1].in_value = NULL;
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if (in)
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{
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if (in) {
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fields[1].in_value = (uint8_t *)in;
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jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
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jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
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} else
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{
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jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
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}
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if (clock_arg)
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jtag_add_runtest(0, TAP_DRPAUSE);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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}
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if (in)
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LOG_DEBUG("out: %8.8x, in: %8.8x, instruction: %i, clock: %i", out, *in, instruction, clock);
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@@ -254,8 +249,7 @@ static int arm720t_arch_state(struct target *target)
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{
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struct arm720t_common *arm720t = target_to_arm720(target);
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static const char *state[] =
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{
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static const char *state[] = {
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"disabled", "enabled"
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};
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@@ -300,16 +294,14 @@ static int arm720t_read_memory(struct target *target,
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struct arm720t_common *arm720t = target_to_arm720(target);
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/* disable cache, but leave MMU enabled */
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if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
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{
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if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
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retval = arm720t_disable_mmu_caches(target, 0, 1, 0);
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if (retval != ERROR_OK)
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return retval;
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}
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retval = arm7_9_read_memory(target, address, size, count, buffer);
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if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
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{
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if (arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) {
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retval = arm720t_enable_mmu_caches(target, 0, 1, 0);
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if (retval != ERROR_OK)
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return retval;
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@@ -342,36 +334,26 @@ static int arm720t_soft_reset_halt(struct target *target)
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.eice_cache->reg_list[EICE_DBG_STAT];
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struct arm *arm = &arm720t->arm7_9_common.arm;
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if ((retval = target_halt(target)) != ERROR_OK)
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{
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retval = target_halt(target);
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if (retval != ERROR_OK)
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return retval;
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}
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long long then = timeval_ms();
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int timeout;
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while (!(timeout = ((timeval_ms()-then) > 1000)))
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{
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if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
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{
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while (!(timeout = ((timeval_ms()-then) > 1000))) {
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if (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0) {
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embeddedice_read_reg(dbg_stat);
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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}
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} else
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{
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break;
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}
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if (debug_level >= 3)
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{
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alive_sleep(100);
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} else
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{
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else
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keep_alive();
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}
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}
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if (timeout)
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{
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if (timeout) {
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LOG_ERROR("Failed to halt CPU after 1 sec");
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return ERROR_TARGET_TIMEOUT;
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}
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@@ -399,10 +381,9 @@ static int arm720t_soft_reset_halt(struct target *target)
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arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
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arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
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if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
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{
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retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
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if (retval != ERROR_OK)
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return retval;
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}
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return ERROR_OK;
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}
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@@ -467,42 +448,35 @@ COMMAND_HANDLER(arm720t_handle_cp15_command)
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if (retval != ERROR_OK)
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return retval;
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if (target->state != TARGET_HALTED)
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{
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if (target->state != TARGET_HALTED) {
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command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
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return ERROR_OK;
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}
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/* one or more argument, access a single register (write if second argument is given */
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if (CMD_ARGC >= 1)
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{
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if (CMD_ARGC >= 1) {
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uint32_t opcode;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], opcode);
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if (CMD_ARGC == 1)
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{
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if (CMD_ARGC == 1) {
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uint32_t value;
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if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
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{
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retval = arm720t_read_cp15(target, opcode, &value);
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if (retval != ERROR_OK) {
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command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
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return ERROR_OK;
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}
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if ((retval = jtag_execute_queue()) != ERROR_OK)
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{
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retval = jtag_execute_queue();
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if (retval != ERROR_OK)
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return retval;
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}
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command_print(CMD_CTX, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
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}
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else if (CMD_ARGC == 2)
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{
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} else if (CMD_ARGC == 2) {
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uint32_t value;
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COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
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if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
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{
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retval = arm720t_write_cp15(target, opcode, value);
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if (retval != ERROR_OK) {
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command_print(CMD_CTX, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
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return ERROR_OK;
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}
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@@ -518,8 +492,7 @@ static int arm720t_mrc(struct target *target, int cpnum,
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uint32_t CRn, uint32_t CRm,
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uint32_t *value)
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{
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if (cpnum!=15)
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{
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if (cpnum != 15) {
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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@@ -536,8 +509,7 @@ static int arm720t_mcr(struct target *target, int cpnum,
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uint32_t CRn, uint32_t CRm,
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uint32_t value)
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{
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if (cpnum!=15)
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{
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if (cpnum != 15) {
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LOG_ERROR("Only cp15 is supported");
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return ERROR_FAIL;
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}
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@@ -576,8 +548,7 @@ static const struct command_registration arm720t_command_handlers[] = {
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};
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/** Holds methods for ARM720 targets. */
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struct target_type arm720t_target =
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{
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struct target_type arm720t_target = {
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.name = "arm720t",
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.poll = arm7_9_poll,
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