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build: cleanup src/target directory

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Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/430
Tested-by: jenkins
This commit is contained in:
Spencer Oliver
2012-02-05 12:03:04 +00:00
parent de0130a0aa
commit 374127301e
107 changed files with 9577 additions and 11917 deletions
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223
src/target/arm946e.c
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@@ -23,6 +23,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
@@ -39,8 +40,8 @@
#define NB_CACHE_WAYS 4
static uint32_t dc = 0x0;
static uint32_t ic = 0x0;
static uint32_t dc;
static uint32_t ic;
/**
* flag to give info about cache manipulation during debug :
@@ -55,8 +56,9 @@ int arm946e_post_debug_entry(struct target *target);
void arm946e_pre_restore_context(struct target *target);
static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *value);
int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e, struct jtag_tap *tap)
int arm946e_init_arch_info(struct target *target,
struct arm946e_common *arm946e,
struct jtag_tap *tap)
{
struct arm7_9_common *arm7_9 = &arm946e->arm7_9_common;
@@ -84,14 +86,14 @@ int arm946e_init_arch_info(struct target *target, struct arm946e_common *arm946e
arm946e_preserve_cache = 0;
/* override hw single-step capability from ARM9TDMI */
//arm7_9->has_single_step = 1;
/* arm7_9->has_single_step = 1; */
return ERROR_OK;
}
static int arm946e_target_create(struct target *target, Jim_Interp *interp)
{
struct arm946e_common *arm946e = calloc(1,sizeof(struct arm946e_common));
struct arm946e_common *arm946e = calloc(1, sizeof(struct arm946e_common));
arm946e_init_arch_info(target, arm946e, target->tap);
@@ -99,7 +101,7 @@ static int arm946e_target_create(struct target *target, Jim_Interp *interp)
}
static int arm946e_verify_pointer(struct command_context *cmd_ctx,
struct arm946e_common *arm946e)
struct arm946e_common *arm946e)
{
if (arm946e->common_magic != ARM946E_COMMON_MAGIC) {
command_print(cmd_ctx, "target is not an ARM946");
@@ -123,10 +125,9 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
uint8_t reg_addr_buf = reg_addr & 0x3f;
uint8_t nr_w_buf = 0;
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
@@ -157,10 +158,9 @@ static int arm946e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, *value);
#endif
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
@@ -177,10 +177,9 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
buf_set_u32(value_buf, 0, 32, value);
if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
{
retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
}
retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
if (retval != ERROR_OK)
return retval;
@@ -203,10 +202,9 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
#endif
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
@@ -214,21 +212,21 @@ int arm946e_write_cp15(struct target *target, int reg_addr, uint32_t value)
uint32_t arm946e_invalidate_whole_dcache(struct target *target)
{
uint32_t csize = 0;
uint32_t shift = 0;
uint32_t cp15_idx, seg, dtag;
int nb_idx, idx = 0;
int retval;
uint32_t csize = 0;
uint32_t shift = 0;
uint32_t cp15_idx, seg, dtag;
int nb_idx, idx = 0;
int retval;
/* Get cache type */
arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
/* Get cache type */
arm946e_read_cp15(target, 0x01, (uint32_t *) &csize);
csize = (csize >> 18) & 0x0F;
csize = (csize >> 18) & 0x0F;
if (csize == 0)
shift = 0;
else
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
/* Cache size, given in bytes */
csize = 1 << (12 + shift);
@@ -236,16 +234,13 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target)
nb_idx = (csize / 32); /* gives nb of lines (indexes) in the cache */
/* Loop for all segmentde (i.e. ways) */
for( seg=0; seg < NB_CACHE_WAYS; seg++)
{
for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
/* Loop for all indexes */
for(idx=0; idx < nb_idx; idx++)
{
for (idx = 0; idx < nb_idx; idx++) {
/* Form and write cp15 index (segment + line idx) */
cp15_idx = seg << 30 | idx << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
@@ -254,21 +249,19 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target)
arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
/* Check cache line VALID bit */
if ( !(dtag >> 4 & 0x1) )
if (!(dtag >> 4 & 0x1))
continue;
/* Clean data cache line */
retval = arm946e_write_cp15(target, 0x35, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR cleaning cache line");
return retval;
}
/* Flush data cache line */
retval = arm946e_write_cp15(target, 0x1a, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing cache line");
return retval;
}
@@ -289,8 +282,7 @@ uint32_t arm946e_invalidate_whole_icache(struct target *target)
* mcr 15, 0, r0, cr7, cr5, {0}
*/
retval = arm946e_write_cp15(target, 0x0f, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing I$");
return retval;
}
@@ -309,10 +301,8 @@ int arm946e_post_debug_entry(struct target *target)
dc = (ctr_reg >> 2) & 0x01;
ic = (ctr_reg >> 12) & 0x01;
if (arm946e_preserve_cache)
{
if (dc == 1)
{
if (arm946e_preserve_cache) {
if (dc == 1) {
/* Clean and flush D$ */
arm946e_invalidate_whole_dcache(target);
@@ -320,8 +310,7 @@ int arm946e_post_debug_entry(struct target *target)
ctr_reg &= ~(1 << 2);
}
if (ic == 1)
{
if (ic == 1) {
/* Flush I$ */
arm946e_invalidate_whole_icache(target);
@@ -331,12 +320,11 @@ int arm946e_post_debug_entry(struct target *target)
/* Write the new configuration */
retval = arm946e_write_cp15(target, 0x02, ctr_reg);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR disabling cache");
return retval;
}
} /* if preserve_cache */
} /* if preserve_cache */
return ERROR_OK;
}
@@ -346,8 +334,7 @@ void arm946e_pre_restore_context(struct target *target)
uint32_t ctr_reg = 0x0;
uint32_t retval;
if (arm946e_preserve_cache)
{
if (arm946e_preserve_cache) {
/* Get the contents of the CTR reg */
arm946e_read_cp15(target, 0x02, (uint32_t *) &ctr_reg);
@@ -355,14 +342,12 @@ void arm946e_pre_restore_context(struct target *target)
* Read-modify-write CP15 test state register
* to reenable I/D-cache linefills
*/
if (dc == 1)
{
if (dc == 1) {
/* Enable D$ */
ctr_reg |= 1 << 2;
}
if (ic == 1)
{
if (ic == 1) {
/* Enable I$ */
ctr_reg |= 1 << 12;
}
@@ -370,14 +355,12 @@ void arm946e_pre_restore_context(struct target *target)
/* Write the new configuration */
retval = arm946e_write_cp15(target, 0x02, ctr_reg);
if (retval != ERROR_OK)
{
LOG_DEBUG("ERROR enabling cache");
}
} /* if preserve_cache */
} /* if preserve_cache */
}
uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
uint32_t size, uint32_t count)
{
uint32_t csize = 0x0;
uint32_t shift = 0;
@@ -386,8 +369,7 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
uint32_t i = 0;
int retval;
for(i = 0; i < count*size; i++)
{
for (i = 0; i < count*size; i++) {
cur_addr = address + i;
/* Get cache type */
@@ -399,14 +381,13 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
if (csize == 0)
shift = 0;
else
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
shift = csize - 0x3; /* Now 0 = 4KB, 1 = 8KB, ... */
csize = 1 << (12 + shift);
set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
for (way = 0; way < NB_CACHE_WAYS; way++)
{
for (way = 0; way < NB_CACHE_WAYS; way++) {
/**
* Find if the affected address is kept in the cache.
* Because JTAG Scan Chain 15 offers limited approach,
@@ -417,8 +398,7 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
/* Form and write cp15 index (segment + line idx) */
cp15_idx = way << 30 | set << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
@@ -427,57 +407,51 @@ uint32_t arm946e_invalidate_dcache(struct target *target, uint32_t address,
arm946e_read_cp15(target, 0x16, (uint32_t *) &dtag);
/* Check cache line VALID bit */
if ( !(dtag >> 4 & 0x1) )
if (!(dtag >> 4 & 0x1))
continue;
/* If line is valid and corresponds to affected address - invalidate it */
if (dtag >> 5 == cur_addr >> 5)
{
if (dtag >> 5 == cur_addr >> 5) {
/* Clean data cache line */
retval = arm946e_write_cp15(target, 0x35, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR cleaning cache line");
return retval;
}
/* Flush data cache line */
retval = arm946e_write_cp15(target, 0x1c, 0x1);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing cache line");
return retval;
}
break;
}
} /* loop through all 4 ways */
} /* loop through all addresses */
} /* loop through all 4 ways */
} /* loop through all addresses */
return ERROR_OK;
}
uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
uint32_t size, uint32_t count)
uint32_t size, uint32_t count)
{
uint32_t cur_addr = 0x0;
uint32_t cp15_idx, set, way, itag;
uint32_t i = 0;
int retval;
for(i = 0; i < count*size; i++)
{
for (i = 0; i < count*size; i++) {
cur_addr = address + i;
set = (cur_addr >> 5) & 0xff; /* set field is 8 bits long */
for (way = 0; way < NB_CACHE_WAYS; way++)
{
for (way = 0; way < NB_CACHE_WAYS; way++) {
/* Form and write cp15 index (segment + line idx) */
cp15_idx = way << 30 | set << 5;
retval = arm946e_write_cp15(target, 0x3a, cp15_idx);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR writing index");
return retval;
}
@@ -486,31 +460,29 @@ uint32_t arm946e_invalidate_icache(struct target *target, uint32_t address,
arm946e_read_cp15(target, 0x17, (uint32_t *) &itag);
/* Check cache line VALID bit */
if ( !(itag >> 4 & 0x1) )
if (!(itag >> 4 & 0x1))
continue;
/* If line is valid and corresponds to affected address - invalidate it */
if (itag >> 5 == cur_addr >> 5)
{
if (itag >> 5 == cur_addr >> 5) {
/* Flush I$ line */
retval = arm946e_write_cp15(target, 0x1d, 0x0);
if (retval != ERROR_OK)
{
if (retval != ERROR_OK) {
LOG_DEBUG("ERROR flushing cache line");
return retval;
}
break;
}
} /* way loop */
} /* addr loop */
} /* way loop */
} /* addr loop */
return ERROR_OK;
}
/** Writes a buffer, in the specified word size, with current MMU settings. */
int arm946e_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
uint32_t size, uint32_t count, const uint8_t *buffer)
{
int retval;
@@ -518,18 +490,14 @@ int arm946e_write_memory(struct target *target, uint32_t address,
/* Invalidate D$ if it is ON */
if (!arm946e_preserve_cache && dc == 1)
{
arm946e_invalidate_dcache(target, address, size, count);
}
/**
* Write memory
*/
if ( ( retval = arm7_9_write_memory(target, address,
size, count, buffer) ) != ERROR_OK )
{
retval = arm7_9_write_memory(target, address, size, count, buffer);
if (retval != ERROR_OK)
return retval;
}
/* *
* Invalidate I$ if it is ON.
@@ -554,26 +522,22 @@ int arm946e_write_memory(struct target *target, uint32_t address,
* If the data is not in the cache, the controller writes to main memory only.
*/
if (!arm946e_preserve_cache && ic == 1)
{
arm946e_invalidate_icache(target, address, size, count);
}
return ERROR_OK;
}
int arm946e_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
LOG_DEBUG("-");
if ( ( retval = arm7_9_read_memory(target, address,
size, count, buffer) ) != ERROR_OK )
{
retval = arm7_9_read_memory(target, address, size, count, buffer);
if (retval != ERROR_OK)
return retval;
}
return ERROR_OK;
}
@@ -589,49 +553,37 @@ COMMAND_HANDLER(arm946e_handle_cp15_command)
if (retval != ERROR_OK)
return retval;
if (target->state != TARGET_HALTED)
{
if (target->state != TARGET_HALTED) {
command_print(CMD_CTX, "target must be stopped for \"%s\" command", CMD_NAME);
return ERROR_OK;
}
/* one or more argument, access a single register (write if second argument is given */
if (CMD_ARGC >= 1)
{
if (CMD_ARGC >= 1) {
uint32_t address;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], address);
if (CMD_ARGC == 1)
{
if (CMD_ARGC == 1) {
uint32_t value;
if ((retval = arm946e_read_cp15(target, address, &value)) != ERROR_OK)
{
command_print(CMD_CTX,
"couldn't access reg %" PRIi32,
address);
retval = arm946e_read_cp15(target, address, &value);
if (retval != ERROR_OK) {
command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
return ERROR_OK;
}
if ((retval = jtag_execute_queue()) != ERROR_OK)
{
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
}
command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32,
address, value);
}
else if (CMD_ARGC == 2)
{
command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
} else if (CMD_ARGC == 2) {
uint32_t value;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
if ((retval = arm946e_write_cp15(target, address, value)) != ERROR_OK)
{
command_print(CMD_CTX,
"couldn't access reg %" PRIi32,
address);
retval = arm946e_write_cp15(target, address, value);
if (retval != ERROR_OK) {
command_print(CMD_CTX, "couldn't access reg %" PRIi32, address);
return ERROR_OK;
}
command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32,
address, value);
command_print(CMD_CTX, "%" PRIi32 ": %8.8" PRIx32, address, value);
}
}
@@ -664,8 +616,7 @@ const struct command_registration arm946e_command_handlers[] = {
};
/** Holds methods for ARM946 targets. */
struct target_type arm946e_target =
{
struct target_type arm946e_target = {
.name = "arm946e",
.poll = arm7_9_poll,
@@ -683,8 +634,8 @@ struct target_type arm946e_target =
.get_gdb_reg_list = arm_get_gdb_reg_list,
//.read_memory = arm7_9_read_memory,
//.write_memory = arm7_9_write_memory,
/* .read_memory = arm7_9_read_memory, */
/* .write_memory = arm7_9_write_memory, */
.read_memory = arm946e_read_memory,
.write_memory = arm946e_write_memory,
@@ -697,8 +648,8 @@ struct target_type arm946e_target =
.add_breakpoint = arm7_9_add_breakpoint,
.remove_breakpoint = arm7_9_remove_breakpoint,
//.add_breakpoint = arm946e_add_breakpoint,
//.remove_breakpoint = arm946e_remove_breakpoint,
/* .add_breakpoint = arm946e_add_breakpoint, */
/* .remove_breakpoint = arm946e_remove_breakpoint, */
.add_watchpoint = arm7_9_add_watchpoint,
.remove_watchpoint = arm7_9_remove_watchpoint,