build: cleanup src/target directory
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
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@@ -323,7 +323,7 @@ static int do_semihosting(struct target *target)
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if (l < s)
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result = -1;
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else {
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retval = target_write_buffer(target, a, s, (void*)arg);
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retval = target_write_buffer(target, a, s, (void *)arg);
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if (retval != ERROR_OK)
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return retval;
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result = 0;
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@@ -392,8 +392,7 @@ static int do_semihosting(struct target *target)
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/* REVISIT this looks wrong ... ARM11 and Cortex-A8
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* should work this way at least sometimes.
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*/
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if (is_arm7_9(target_to_arm7_9(target)))
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{
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if (is_arm7_9(target_to_arm7_9(target))) {
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uint32_t spsr;
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/* return value in R0 */
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@@ -402,7 +401,7 @@ static int do_semihosting(struct target *target)
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/* LR --> PC */
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buf_set_u32(arm->core_cache->reg_list[15].value, 0, 32,
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buf_get_u32(arm_reg_current(arm,14)->value, 0, 32));
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buf_get_u32(arm_reg_current(arm, 14)->value, 0, 32));
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arm->core_cache->reg_list[15].dirty = 1;
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/* saved PSR --> current PSR */
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@@ -418,9 +417,7 @@ static int do_semihosting(struct target *target)
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if (spsr & 0x20)
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arm->core_state = ARM_STATE_THUMB;
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}
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else
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{
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} else {
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/* resume execution, this will be pc+2 to skip over the
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* bkpt instruction */
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@@ -454,8 +451,7 @@ int arm_semihosting(struct target *target, int *retval)
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if (!arm->is_semihosting)
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return 0;
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if (is_arm7_9(target_to_arm7_9(target)))
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{
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if (is_arm7_9(target_to_arm7_9(target))) {
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if (arm->core_mode != ARM_MODE_SVC)
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return 0;
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@@ -510,9 +506,7 @@ int arm_semihosting(struct target *target, int *retval)
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if (insn != 0xEF123456)
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return 0;
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}
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}
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else if (is_armv7m(target_to_armv7m(target)))
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{
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} else if (is_armv7m(target_to_armv7m(target))) {
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uint16_t insn;
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if (target->debug_reason != DBG_REASON_BREAKPOINT)
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@@ -529,9 +523,7 @@ int arm_semihosting(struct target *target, int *retval)
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/* bkpt 0xAB */
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if (insn != 0xBEAB)
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return 0;
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}
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else
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{
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} else {
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LOG_ERROR("Unsupported semi-hosting Target");
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return 0;
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}
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