moves handling of problems with resetting into the halted state
into the target implementation. Also target_process_reset() is now simpler and has error handling, e.g. if assert reset fails, then target_process_reset() will propagate that error. cmd_ctx was passed in to examine(), which is wrong - removed that. git-svn-id: svn://svn.berlios.de/openocd/trunk@887 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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@@ -821,12 +821,26 @@ int arm7_9_assert_reset(target_t *target)
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int arm7_9_deassert_reset(target_t *target)
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{
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int retval=ERROR_OK;
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LOG_DEBUG("target->state: %s", target_state_strings[target->state]);
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/* deassert reset lines */
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jtag_add_reset(0, 0);
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return ERROR_OK;
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if ((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0)
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{
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/* set up embedded ice registers again */
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if ((retval=target->type->examine(target))!=ERROR_OK)
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return retval;
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if (target->reset_halt)
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{
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/* halt the CPU as embedded ice was not set up in reset */
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if ((retval=target->type->halt(target))!=ERROR_OK)
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return retval;
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}
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}
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return retval;
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}
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int arm7_9_clear_halt(target_t *target)
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@@ -961,6 +975,12 @@ int arm7_9_soft_reset_halt(struct target_s *target)
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int arm7_9_halt(target_t *target)
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{
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if ((target->state==TARGET_RESET)&&((jtag_reset_config & RESET_SRST_PULLS_TRST)!=0))
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{
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LOG_WARNING("arm7/9 can't halt a target in reset if srst pulls trst - halting after reset");
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return ERROR_OK;
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}
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
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