- endianess fixes everywhere but in the flash code. flashing might still be broken on big-endian targets and/or hosts
- added access to ARM920T vector catch register (via generic register mechanism) - don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache - read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands) - memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes) - made in_handler independent from in field (makes the handler more flexible) - added timeout to ft2232 when using D2XX library - fixed STR7x protection bit handling on second bank (thanks to Bernard) - added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen) - fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen) git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
@@ -51,7 +51,6 @@ int arm7tdmi_quit();
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/* target function declarations */
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enum target_state arm7tdmi_poll(struct target_s *target);
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int arm7tdmi_halt(target_t *target);
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int arm7tdmi_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
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target_type_t arm7tdmi_target =
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{
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@@ -152,8 +151,7 @@ int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
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u8 out_buf[4];
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u8 breakpoint_buf;
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out = flip_u32(out, 32);
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buf_set_u32(out_buf, 0, 32, out);
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buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
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buf_set_u32(&breakpoint_buf, 0, 1, breakpoint);
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jtag_add_end_state(TAP_PD);
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@@ -174,18 +172,17 @@ int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
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fields[1].num_bits = 32;
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fields[1].out_value = out_buf;
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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if (in)
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{
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fields[1].in_value = (u8*)in;
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fields[1].in_handler = arm_jtag_buf_to_u32_flip;
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fields[1].in_handler_priv = in;
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} else
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}
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else
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{
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fields[1].in_value = NULL;
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fields[1].in_handler = NULL;
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fields[1].in_handler_priv = NULL;
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}
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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@@ -195,24 +192,21 @@ int arm7tdmi_clock_out(arm_jtag_t *jtag_info, u32 out, u32 *in, int breakpoint)
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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{
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char* in_string;
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jtag_execute_queue();
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if (in)
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{
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in_string = buf_to_char((u8*)in, 32);
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DEBUG("out: 0x%8.8x, in: %s", flip_u32(out, 32), in_string);
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free(in_string);
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DEBUG("out: 0x%8.8x, in: 0x%8.8x", out, *in);
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}
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else
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DEBUG("out: 0x%8.8x", flip_u32(out, 32));
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DEBUG("out: 0x%8.8x", out);
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}
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#endif
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return ERROR_OK;
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}
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/* put an instruction in the ARM7TDMI pipeline, and optionally read data */
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/* clock the target, reading the databus */
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int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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{
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scan_field_t fields[2];
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@@ -235,7 +229,7 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].out_mask = NULL;
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fields[1].in_value = (u8*)in;
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fields[1].in_value = NULL;
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fields[1].in_handler = arm_jtag_buf_to_u32_flip;
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fields[1].in_handler_priv = in;
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fields[1].in_check_value = NULL;
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@@ -247,14 +241,80 @@ int arm7tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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{
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char* in_string;
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jtag_execute_queue();
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if (in)
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{
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in_string = buf_to_char((u8*)in, 32);
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DEBUG("in: %s", in_string);
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free(in_string);
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DEBUG("in: 0x%8.8x", *in);
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}
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else
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{
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ERROR("BUG: called with in == NULL");
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}
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}
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#endif
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return ERROR_OK;
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}
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/* clock the target, and read the databus
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* the *in pointer points to a buffer where elements of 'size' bytes
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* are stored in big (be==1) or little (be==0) endianness
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*/
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int arm7tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
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{
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scan_field_t fields[2];
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jtag_add_end_state(TAP_PD);
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arm_jtag_scann(jtag_info, 0x1);
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arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
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fields[0].device = jtag_info->chain_pos;
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fields[0].num_bits = 1;
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fields[0].out_value = NULL;
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fields[0].out_mask = NULL;
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fields[0].in_value = NULL;
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fields[0].in_check_value = NULL;
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fields[0].in_check_mask = NULL;
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fields[0].in_handler = NULL;
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fields[0].in_handler_priv = NULL;
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fields[1].device = jtag_info->chain_pos;
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fields[1].num_bits = 32;
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fields[1].out_value = NULL;
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fields[1].out_mask = NULL;
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fields[1].in_value = NULL;
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switch (size)
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{
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case 4:
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fields[1].in_handler = (be) ? arm_jtag_buf_to_be32_flip : arm_jtag_buf_to_le32_flip;
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break;
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case 2:
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fields[1].in_handler = (be) ? arm_jtag_buf_to_be16_flip : arm_jtag_buf_to_le16_flip;
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break;
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case 1:
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fields[1].in_handler = arm_jtag_buf_to_8_flip;
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break;
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}
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fields[1].in_handler_priv = in;
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fields[1].in_check_value = NULL;
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fields[1].in_check_mask = NULL;
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jtag_add_dr_scan(2, fields, -1);
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jtag_add_runtest(0, -1);
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#ifdef _DEBUG_INSTRUCTION_EXECUTION_
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{
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jtag_execute_queue();
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if (in)
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{
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DEBUG("in: 0x%8.8x", *in);
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}
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else
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{
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ERROR("BUG: called with in == NULL");
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}
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}
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#endif
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@@ -334,6 +394,50 @@ void arm7tdmi_read_core_regs(target_t *target, u32 mask, u32* core_regs[16])
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}
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void arm7tdmi_read_core_regs_target_buffer(target_t *target, u32 mask, void* buffer, int size)
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{
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int i;
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/* get pointers to arch-specific information */
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armv4_5_common_t *armv4_5 = target->arch_info;
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arm7_9_common_t *arm7_9 = armv4_5->arch_info;
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arm_jtag_t *jtag_info = &arm7_9->jtag_info;
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int be = (target->endianness == TARGET_BIG_ENDIAN) ? 1 : 0;
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u32 *buf_u32 = buffer;
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u16 *buf_u16 = buffer;
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u8 *buf_u8 = buffer;
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/* STMIA r0-15, [r0] at debug speed
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* register values will start to appear on 4th DCLK
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*/
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arm7tdmi_clock_out(jtag_info, ARMV4_5_STMIA(0, mask & 0xffff, 0, 0), NULL, 0);
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/* fetch NOP, STM in DECODE stage */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
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/* fetch NOP, STM in EXECUTE stage (1st cycle) */
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arm7tdmi_clock_out(jtag_info, ARMV4_5_NOP, NULL, 0);
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for (i = 0; i <= 15; i++)
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{
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/* nothing fetched, STM still in EXECUTE (1+i cycle), read databus */
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if (mask & (1 << i))
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{
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switch (size)
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{
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case 4:
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arm7tdmi_clock_data_in_endianness(jtag_info, buf_u32++, 4, be);
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break;
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case 2:
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arm7tdmi_clock_data_in_endianness(jtag_info, buf_u16++, 2, be);
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break;
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case 1:
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arm7tdmi_clock_data_in_endianness(jtag_info, buf_u8++, 1, be);
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break;
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}
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}
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}
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}
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void arm7tdmi_read_xpsr(target_t *target, u32 *xpsr, int spsr)
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{
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/* get pointers to arch-specific information */
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@@ -684,6 +788,7 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, int c
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arm7_9->examine_debug_reason = arm7tdmi_examine_debug_reason;
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arm7_9->change_to_arm = arm7tdmi_change_to_arm;
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arm7_9->read_core_regs = arm7tdmi_read_core_regs;
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arm7_9->read_core_regs_target_buffer = arm7tdmi_read_core_regs_target_buffer;
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arm7_9->read_xpsr = arm7tdmi_read_xpsr;
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arm7_9->write_xpsr = arm7tdmi_write_xpsr;
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