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- endianess fixes everywhere but in the flash code. flashing might still be broken on big-endian targets and/or hosts

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- added access to ARM920T vector catch register (via generic register mechanism)
- don't disable linefills on ARM920T cores - this lead to lockups when accessing lines already contained in cache
- read content of ARM920T cache and tlb into file (arm920t read_flash/read_mmu commands)
- memory reading improved on ARM7/9, can be further accelerated with new "arm7_9 fast_memory_access enable" command (renamed from fast_writes)
- made in_handler independent from in field (makes the handler more flexible)
- added timeout to ft2232 when using D2XX library
- fixed STR7x protection bit handling on second bank (thanks to Bernard)
- added support for using the OpenOCD on AT91RM9200 systems (thanks to Anders Larsen)
- fixed AT91SAM7 flash handling when not running from 32kHz clock (thanks to Anders Larsen)


git-svn-id: svn://svn.berlios.de/openocd/trunk@90 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2006-08-31 12:41:49 +00:00
parent da9eedc0f2
commit 3acb107b9a
27 changed files with 1331 additions and 300 deletions
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29
src/target/armv4_5_mmu.c
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@@ -25,6 +25,7 @@
#include "log.h"
#include "command.h"
#include "armv4_5_mmu.h"
#include "target.h"
#include <stdlib.h>
@@ -46,6 +47,7 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
armv4_5_mmu_read_physical(target, armv4_5_mmu,
(ttb & 0xffffc000) | ((va & 0xfff00000) >> 18),
4, 1, (u8*)&first_lvl_descriptor);
first_lvl_descriptor = target_buffer_get_u32(target, (u8*)&first_lvl_descriptor);
DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
@@ -80,16 +82,17 @@ u32 armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu
(first_lvl_descriptor & 0xfffffc00) | ((va & 0x000ff000) >> 10),
4, 1, (u8*)&second_lvl_descriptor);
}
if ((first_lvl_descriptor & 0x3) == 3)
else if ((first_lvl_descriptor & 0x3) == 3)
{
/* fine page table */
armv4_5_mmu_read_physical(target, armv4_5_mmu,
(first_lvl_descriptor & 0xfffff000) | ((va & 0x000ffc00) >> 8),
4, 1, (u8*)&second_lvl_descriptor);
}
DEBUG("2nd lvl desc: %8.8x", first_lvl_descriptor);
second_lvl_descriptor = target_buffer_get_u32(target, (u8*)&second_lvl_descriptor);
DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
if ((second_lvl_descriptor & 0x3) == 0)
{
@@ -286,17 +289,17 @@ int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, ch
switch (size)
{
case 4:
output_len += snprintf(output + output_len, 128 - output_len, "%8.8x ", ((u32*)buffer)[i]);
output_len += snprintf(output + output_len, 128 - output_len, "%8.8x ", target_buffer_get_u32(target, &buffer[i*4]));
break;
case 2:
output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", ((u16*)buffer)[i]);
output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2]));
break;
case 1:
output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", ((u8*)buffer)[i]);
output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]);
break;
}
if ((i%8 == 7) || (i == count - 1))
if ((i % 8 == 7) || (i == count - 1))
{
command_print(cmd_ctx, output);
output_len = 0;
@@ -313,6 +316,7 @@ int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, ch
u32 address = 0;
u32 value = 0;
int retval;
u8 value_buf[4];
if (target->state != TARGET_HALTED)
{
@@ -329,13 +333,16 @@ int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, ch
switch (cmd[2])
{
case 'w':
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, (u8*)&value);
target_buffer_set_u32(target, value_buf, value);
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, value_buf);
break;
case 'h':
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, (u8*)&value);
target_buffer_set_u16(target, value_buf, value);
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, value_buf);
break;
case 'b':
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, (u8*)&value);
value_buf[0] = value;
retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, value_buf);
break;
default:
return ERROR_OK;