ARM11: remove old R0..R15/CPSR code

This finishes the basic switchover to the new register code,
for everything except the debug registers.  (And maybe we
shouldn't have a cache for *those* which works this way...)

The context save/restore code now uses the new code, but
it's in a slightly different sequence.  That should be fine
since the R0/PC/CPSR stuff is all that really matters (and
if we can update those, we can update the rest).

Now there's no longer a way any code can be confused about
which copy of "r1" (etc) to use.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>

src/target/arm11.h

@@ -26,8 +26,7 @@
 #include "armv4_5.h"
 #include "arm_dpm.h"
 
-/* TEMPORARY -- till we switch to the shared infrastructure */
-#define ARM11_REGCACHE_COUNT		20
+#define ARM11_REGCACHE_COUNT		3
 
 #define ARM11_TAP_DEFAULT			TAP_INVALID
 
@@ -70,7 +69,7 @@ struct arm11_common
 
 	bool	simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt */
 
-	/** \name Shadow registers to save processor state */
+	/** \name Shadow registers to save debug state */
 	/*@{*/
 
 	struct reg *	reg_list;							/**< target register list */