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use COMMAND_PARSE_ENABLE macro where appropriate

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Updates all command parsing of simple "enable" and "disable" arguments.
A few case in the tree use a tri-state or extended arguments, which
cannot use this simple macro.

Simlifies the xscale icache/dcache command handler logic.
This commit is contained in:
Zachary T Welch
2009-11-18 05:36:18 -08:00
parent 75a37eb5b3
commit 410fab9ea8
6 changed files with 41 additions and 158 deletions
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45
src/target/arm7_9_common.c
View File

@@ -2870,20 +2870,7 @@ COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
}
if (CMD_ARGC > 0)
{
if (strcmp("enable", CMD_ARGV[0]) == 0)
{
arm7_9->use_dbgrq = 1;
}
else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
arm7_9->use_dbgrq = 0;
}
else
{
command_print(CMD_CTX, "usage: arm7_9 dbgrq <enable | disable>");
}
}
COMMAND_PARSE_ENABLE(CMD_ARGV[0],arm7_9->use_dbgrq);
command_print(CMD_CTX, "use of EmbeddedICE dbgrq instead of breakpoint for target halt %s", (arm7_9->use_dbgrq) ? "enabled" : "disabled");
@@ -2902,20 +2889,7 @@ COMMAND_HANDLER(handle_arm7_9_fast_memory_access_command)
}
if (CMD_ARGC > 0)
{
if (strcmp("enable", CMD_ARGV[0]) == 0)
{
arm7_9->fast_memory_access = 1;
}
else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
arm7_9->fast_memory_access = 0;
}
else
{
command_print(CMD_CTX, "usage: arm7_9 fast_memory_access <enable | disable>");
}
}
COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->fast_memory_access);
command_print(CMD_CTX, "fast memory access is %s", (arm7_9->fast_memory_access) ? "enabled" : "disabled");
@@ -2934,20 +2908,7 @@ COMMAND_HANDLER(handle_arm7_9_dcc_downloads_command)
}
if (CMD_ARGC > 0)
{
if (strcmp("enable", CMD_ARGV[0]) == 0)
{
arm7_9->dcc_downloads = 1;
}
else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
arm7_9->dcc_downloads = 0;
}
else
{
command_print(CMD_CTX, "usage: arm7_9 dcc_downloads <enable | disable>");
}
}
COMMAND_PARSE_ENABLE(CMD_ARGV[0], arm7_9->dcc_downloads);
command_print(CMD_CTX, "dcc downloads are %s", (arm7_9->dcc_downloads) ? "enabled" : "disabled");

21
src/target/etm.c
View File

@@ -1214,25 +1214,14 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
return ERROR_INVALID_ARGUMENTS;
}
if (strcmp(CMD_ARGV[2], "enable") == 0)
bool etmv1_cycle_accurate;
COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
if (etmv1_cycle_accurate)
tracemode |= ETMV1_CYCLE_ACCURATE;
else if (strcmp(CMD_ARGV[2], "disable") == 0)
tracemode |= 0;
else
{
command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[2]);
return ERROR_INVALID_ARGUMENTS;
}
if (strcmp(CMD_ARGV[3], "enable") == 0)
bool etmv1_branch_output;
COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
tracemode |= ETMV1_BRANCH_OUTPUT;
else if (strcmp(CMD_ARGV[3], "disable") == 0)
tracemode |= 0;
else
{
command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[3]);
return ERROR_INVALID_ARGUMENTS;
}
/* IGNORED:
* - CPRT tracing (coprocessor register transfers)

61
src/target/xscale.c
View File

@@ -3130,16 +3130,13 @@ COMMAND_HANDLER(xscale_handle_mmu_command)
if (CMD_ARGC >= 1)
{
if (strcmp("enable", CMD_ARGV[0]) == 0)
{
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
if (enable)
xscale_enable_mmu_caches(target, 1, 0, 0);
xscale->armv4_5_mmu.mmu_enabled = 1;
}
else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
else
xscale_disable_mmu_caches(target, 1, 0, 0);
xscale->armv4_5_mmu.mmu_enabled = 0;
}
xscale->armv4_5_mmu.mmu_enabled = enable;
}
command_print(CMD_CTX, "mmu %s", (xscale->armv4_5_mmu.mmu_enabled) ? "enabled" : "disabled");
@@ -3151,10 +3148,8 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
{
struct target *target = get_current_target(CMD_CTX);
struct xscale_common *xscale = target_to_xscale(target);
int icache = 0, dcache = 0;
int retval;
retval = xscale_verify_pointer(CMD_CTX, xscale);
int retval = xscale_verify_pointer(CMD_CTX, xscale);
if (retval != ERROR_OK)
return retval;
@@ -3164,38 +3159,28 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
return ERROR_OK;
}
if (strcmp(CMD_NAME, "icache") == 0)
icache = 1;
else if (strcmp(CMD_NAME, "dcache") == 0)
dcache = 1;
bool icache;
COMMAND_PARSE_BOOL(CMD_NAME, icache, "icache", "dcache");
if (CMD_ARGC >= 1)
{
if (strcmp("enable", CMD_ARGV[0]) == 0)
{
xscale_enable_mmu_caches(target, 0, dcache, icache);
if (icache)
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 1;
else if (dcache)
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 1;
}
else if (strcmp("disable", CMD_ARGV[0]) == 0)
{
xscale_disable_mmu_caches(target, 0, dcache, icache);
if (icache)
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
else if (dcache)
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
}
bool enable;
COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
if (enable)
xscale_enable_mmu_caches(target, 1, 0, 0);
else
xscale_disable_mmu_caches(target, 1, 0, 0);
if (icache)
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
else
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
}
if (icache)
command_print(CMD_CTX, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache)
command_print(CMD_CTX, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
bool enabled = icache ?
xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled :
xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled;
const char *msg = enabled ? "enabled" : "disabled";
command_print(CMD_CTX, "%s %s", CMD_NAME, msg);
return ERROR_OK;
}