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aarch64: fix cache identification

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Use correct instructions to access CLIDR, CSSELR and CCSIDR.

Change-Id: I319b96c03a44fdb59fcb18a00f816f6af0261f0a
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
This commit is contained in:
Matthias Welwarsky
2016-09-16 11:49:57 +02:00
parent 7eb95b1d72
commit 4314624669
2 changed files with 18 additions and 28 deletions
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2
src/target/aarch64.c
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@@ -1235,10 +1235,8 @@ static int aarch64_post_debug_entry(struct target *target)
LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
aarch64->system_control_reg_curr = aarch64->system_control_reg;
#if 0
if (armv8->armv8_mmu.armv8_cache.ctype == -1)
armv8_identify_cache(target);
#endif
armv8->armv8_mmu.mmu_enabled =
(aarch64->system_control_reg & 0x1U) ? 1 : 0;