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esirisc: support eSi-RISC targets

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eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
2018-08-28 17:18:01 -07:00
committed by Matthias Welwarsky
parent e72b2601e7
commit 4ab75a3634
17 changed files with 3496 additions and 9 deletions
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10
src/target/Makefile.am
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@@ -23,6 +23,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
$(NDS32_SRC) \
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(ESIRISC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
@@ -139,6 +140,10 @@ INTEL_IA32_SRC = \
%D%/lakemont.c \
%D%/x86_32_common.c
ESIRISC_SRC = \
%D%/esirisc.c \
%D%/esirisc_jtag.c
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
@@ -218,7 +223,10 @@ INTEL_IA32_SRC = \
%D%/stm8.h \
%D%/lakemont.h \
%D%/x86_32_common.h \
%D%/arm_cti.h
%D%/arm_cti.h \
%D%/esirisc.h \
%D%/esirisc_jtag.h \
%D%/esirisc_regs.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am