esirisc: support eSi-RISC targets
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
This commit is contained in:
Steven Stallion
committed by
Matthias Welwarsky
Matthias Welwarsky
parent
e72b2601e7
commit
4ab75a3634
184
src/target/esirisc_regs.h
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184
src/target/esirisc_regs.h
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/***************************************************************************
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* Copyright (C) 2018 by Square, Inc. *
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* Steven Stallion <stallion@squareup.com> *
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* James Zhao <hjz@squareup.com> *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_TARGET_ESIRISC_REGS_H
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#define OPENOCD_TARGET_ESIRISC_REGS_H
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enum esirisc_reg_num {
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ESIRISC_SP,
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ESIRISC_RA,
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ESIRISC_R2,
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ESIRISC_R3,
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ESIRISC_R4,
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ESIRISC_R5,
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ESIRISC_R6,
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ESIRISC_R7,
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ESIRISC_R8,
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ESIRISC_R9,
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ESIRISC_R10,
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ESIRISC_R11,
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ESIRISC_R12,
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ESIRISC_R13,
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ESIRISC_R14,
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ESIRISC_R15,
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ESIRISC_R16,
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ESIRISC_R17,
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ESIRISC_R18,
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ESIRISC_R19,
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ESIRISC_R20,
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ESIRISC_R21,
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ESIRISC_R22,
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ESIRISC_R23,
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ESIRISC_R24,
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ESIRISC_R25,
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ESIRISC_R26,
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ESIRISC_R27,
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ESIRISC_R28,
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ESIRISC_R29,
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ESIRISC_R30,
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ESIRISC_R31,
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ESIRISC_V0,
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ESIRISC_V1,
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ESIRISC_V2,
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ESIRISC_V3,
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ESIRISC_V4,
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ESIRISC_V5,
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ESIRISC_V6,
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ESIRISC_V7,
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ESIRISC_V8,
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ESIRISC_V9,
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ESIRISC_V10,
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ESIRISC_V11,
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ESIRISC_V12,
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ESIRISC_V13,
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ESIRISC_V14,
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ESIRISC_V15,
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ESIRISC_V16,
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ESIRISC_V17,
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ESIRISC_V18,
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ESIRISC_V19,
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ESIRISC_V20,
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ESIRISC_V21,
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ESIRISC_V22,
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ESIRISC_V23,
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ESIRISC_V24,
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ESIRISC_V25,
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ESIRISC_V26,
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ESIRISC_V27,
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ESIRISC_V28,
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ESIRISC_V29,
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ESIRISC_V30,
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ESIRISC_V31,
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ESIRISC_A0,
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ESIRISC_A1,
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ESIRISC_A2,
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ESIRISC_A3,
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ESIRISC_A4,
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ESIRISC_A5,
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ESIRISC_A6,
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ESIRISC_A7,
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ESIRISC_PC,
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ESIRISC_CAS,
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ESIRISC_TC,
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ESIRISC_ETA,
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ESIRISC_ETC,
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ESIRISC_EPC,
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ESIRISC_ECAS,
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ESIRISC_EID,
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ESIRISC_ED,
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ESIRISC_IP,
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ESIRISC_IM,
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ESIRISC_IS,
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ESIRISC_IT,
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ESIRISC_NUM_REGS,
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};
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/* CSR Banks */
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#define CSR_THREAD 0x00
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#define CSR_INTERRUPT 0x01
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#define CSR_DEBUG 0x04
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#define CSR_CONFIG 0x05
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#define CSR_TRACE 0x09
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/* Thread CSRs */
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#define CSR_THREAD_TC 0x00 /* Thread Control */
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#define CSR_THREAD_PC 0x01 /* Program Counter */
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#define CSR_THREAD_CAS 0x02 /* Comparison & Arithmetic Status */
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#define CSR_THREAD_AC 0x03 /* Arithmetic Control */
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#define CSR_THREAD_LF 0x04 /* Locked Flag */
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#define CSR_THREAD_LA 0x05 /* Locked Address */
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#define CSR_THREAD_ETA 0x07 /* Exception Table Address */
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#define CSR_THREAD_ETC 0x08 /* Exception TC */
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#define CSR_THREAD_EPC 0x09 /* Exception PC */
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#define CSR_THREAD_ECAS 0x0a /* Exception CAS */
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#define CSR_THREAD_EID 0x0b /* Exception ID */
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#define CSR_THREAD_ED 0x0c /* Exception Data */
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/* Interrupt CSRs */
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#define CSR_INTERRUPT_IP 0x00 /* Interrupt Pending */
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#define CSR_INTERRUPT_IA 0x01 /* Interrupt Acknowledge */
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#define CSR_INTERRUPT_IM 0x02 /* Interrupt Mask */
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#define CSR_INTERRUPT_IS 0x03 /* Interrupt Sense */
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#define CSR_INTERRUPT_IT 0x04 /* Interrupt Trigger */
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/* Debug CSRs */
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#define CSR_DEBUG_DC 0x00 /* Debug Control */
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#define CSR_DEBUG_IBC 0x01 /* Instruction Breakpoint Control */
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#define CSR_DEBUG_DBC 0x02 /* Data Breakpoint Control */
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#define CSR_DEBUG_HWDC 0x03 /* Hardware Debug Control */
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#define CSR_DEBUG_DBS 0x04 /* Data Breakpoint Size */
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#define CSR_DEBUG_DBR 0x05 /* Data Breakpoint Range */
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#define CSR_DEBUG_IBAn 0x08 /* Instruction Breakpoint Address [0..7] */
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#define CSR_DEBUG_DBAn 0x10 /* Data Breakpoint Address [0..7] */
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/* Configuration CSRs */
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#define CSR_CONFIG_ARCH0 0x00 /* Architectural Configuration 0 */
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#define CSR_CONFIG_ARCH1 0x01 /* Architectural Configuration 1 */
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#define CSR_CONFIG_ARCH2 0x02 /* Architectural Configuration 2 */
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#define CSR_CONFIG_ARCH3 0x03 /* Architectural Configuration 3 */
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#define CSR_CONFIG_MEM 0x04 /* Memory Configuration */
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#define CSR_CONFIG_IC 0x05 /* Instruction Cache Configuration */
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#define CSR_CONFIG_DC 0x06 /* Data Cache Configuration */
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#define CSR_CONFIG_INT 0x07 /* Interrupt Configuration */
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#define CSR_CONFIG_ISAn 0x08 /* Instruction Set Configuration [0..6] */
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#define CSR_CONFIG_DBG 0x0f /* Debug Configuration */
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#define CSR_CONFIG_MID 0x10 /* Manufacturer ID */
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#define CSR_CONFIG_REV 0x11 /* Revision Number */
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#define CSR_CONFIG_MPID 0x12 /* Mulitprocessor ID */
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#define CSR_CONFIG_FREQn 0x13 /* Frequency [0..2] */
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#define CSR_CONFIG_TRACE 0x16 /* Trace Configuration */
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/* Trace CSRs */
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#define CSR_TRACE_CONTROL 0x00
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#define CSR_TRACE_STATUS 0x01
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#define CSR_TRACE_BUFFER_START 0x02
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#define CSR_TRACE_BUFFER_END 0x03
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#define CSR_TRACE_BUFFER_CUR 0x04
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#define CSR_TRACE_TRIGGER 0x05
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#define CSR_TRACE_START_DATA 0x06
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#define CSR_TRACE_START_MASK 0x07
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#define CSR_TRACE_STOP_DATA 0x08
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#define CSR_TRACE_STOP_MASK 0x09
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#define CSR_TRACE_DELAY 0x0a
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#endif /* OPENOCD_TARGET_ESIRISC_REGS_H */
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