esirisc: support eSi-RISC targets

eSi-RISC is a highly configurable microprocessor architecture for
embedded systems provided by EnSilica. This patch adds support for
32-bit targets and also includes an internal flash driver and
uC/OS-III RTOS support. This is a non-traditional target and required
a number of additional changes to support non-linear register numbers
and the 'p' packet in RTOS support for proper integration into
EnSilica's GDB port.

Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f
Signed-off-by: Steven Stallion <stallion@squareup.com>
Reviewed-on: http://openocd.zylin.com/4660
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

tcl/target/esi32xx.cfg

@@ -0,0 +1,36 @@
+#
+# EnSilica eSi-32xx SoC (eSi-RISC Family)
+# http://www.ensilica.com/risc-ip/
+#
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME esi32xx
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x11234001
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME esirisc -chain-position $_CHIPNAME.cpu
+
+# Targets with the UNIFIED_ADDRESS_SPACE option disabled should set
+# CACHEARCH to 'harvard'. By default, 'von_neumann' is assumed.
+if { [info exists CACHEARCH] } {
+    $_TARGETNAME esirisc cache_arch $CACHEARCH
+}
+
+adapter_khz 2000
+
+reset_config none
+
+# The default linker scripts provided by the eSi-RISC toolchain do not
+# specify attributes on memory regions, which results in incorrect
+# application of software breakpoints by GDB.
+gdb_breakpoint_override hard