From 4e493229c6c2d84e8f52341be0328ce31e57a6f2 Mon Sep 17 00:00:00 2001
From: Ashi Gupta <quic_ashig@quicinc.com>
Date: Fri, 10 Jan 2025 15:35:14 +0530
Subject: [PATCH] tcl/target: Added target configuration for Qualcomm QCS6490
 IOT Processors.

QCS6490 and QCM6490 are 6nm processors designed for enterprise and IOT
applications featuring global 5G and Wi-Fi 6E support with similar
architecture.

This configuration file will allow debugging applications on these
processors.

Verified with Olimex(ARM-USB-OCD-H):
openocd -f tcl/interface/ftdi/olimex-arm-usb-ocd-h.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>

and Jlink:
openocd -f tcl/interface/jlink.cfg
-c 'transport select jtag'
-f <path_to_qcs6490_cfg>

Change-Id: I05e923293134eaa9b70d3cf0d18efac9a024b6c7
Signed-off-by: Ashi Gupta <quic_ashig@quicinc.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8615
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
---
 tcl/target/qualcomm/qcs6490.cfg | 48 +++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 tcl/target/qualcomm/qcs6490.cfg

diff --git a/tcl/target/qualcomm/qcs6490.cfg b/tcl/target/qualcomm/qcs6490.cfg
new file mode 100644
index 000000000..d12708c8a
--- /dev/null
+++ b/tcl/target/qualcomm/qcs6490.cfg
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# The QCS6490/QCM6490 is a 6nm processor designed for enterprise and Internet of Things (IOT) applications,
+# featuring global 5G and Wi-Fi 6E support
+#
+# Product Page:
+# https://www.qualcomm.com/products/internet-of-things/industrial/building-enterprise/qcs6490
+# https://www.qualcomm.com/products/internet-of-things/industrial/building-enterprise/qcm6490
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME QCS6490
+}
+
+if { [info exists ENDIAN] } {
+   set _ENDIAN $ENDIAN
+} else {
+   set _ENDIAN little
+}
+
+adapter speed 500
+reset_config trst_and_srst
+
+# Set CUP TAP ID based on protocol selection
+if { [using_jtag] } {
+        set _CPUTAPID 0x5ba00477
+} else {
+        set _CPUTAPID 0x5ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID -irlen 4
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -ignore-syspwrupack
+
+cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -baseaddr 0x87020000 -ap-num 1
+
+target create $_CHIPNAME.cpu0 aarch64 -endian $_ENDIAN -dap $_CHIPNAME.dap -coreid 0 \
+   -dbgbase 0x87010000 -cti $_CHIPNAME.cti -event reset-assert-post { dap init }
+
+$_CHIPNAME.cpu0 configure -event examine-end {
+   eval $_CHIPNAME.cpu0 arp_halt
+}
+
+# Default breakpoints to hardware breakpoints
+gdb_breakpoint_override hard